Introduction | |
A Brief History | |
Book Summary | |
MOS Transistors | |
CMOS Logic | |
CMOS Fabrication and Layout | |
Design Partitioning | |
Example: A Simple MIPS Microprocessor | |
Logic Design | |
Circuit Design | |
Physical Design | |
Design Verification | |
Fabrication, Packaging, and Testing | |
Summary | |
Exercises | |
MOS Transistor Theory | |
Introduction | |
Ideal I-V Characteristics | |
C-V Characteristics | |
Nonideal I-V Effects | |
DC Transfer Characteristics | |
Switch-Level RC Delay Models | |
Pitfalls and Fallacies | |
Summary | |
Exercises | |
CMOS Processing Technology | |
Introduction | |
CMOS Technologies | |
Layout Design Rules | |
CMOS Process Enhancements | |
Technology Related CAD Issues | |
Manufacturing Issues | |
Pitfalls and Fallacies | |
Historical Perspective | |
Summary | |
Exercises | |
References | |
Circuit Characterization and Performance Estimation | |
Introduction | |
Delay Estimation | |
Logical Effort and Transistor Sizing | |
Power Disruption | |
Interconnect | |
Wire Engineering | |
Design Margin | |
Reliability | |
Scaling | |
Pitfalls and Fallacies | |
Historical Perspective | |
Summary | |
Exercises | |
Circuit Simulation | |
Introduction | |
A SPICE Tutorial | |
Device Models | |
Device Characterization | |
Interconnect Simulation | |
Pitfalls and Fallacies | |
Summary | |
Exercises | |
Combinational Circuit Design | |
Introduction | |
Circuit Families | |
Circuit Pitfalls | |
More Circuit Families | |
Comparison of Circuit Families | |
Silicon-on-Insulator Circuit Design | |
Pitfalls and Fallacies | |
Historical Perspective | |
Summary | |
Exercises | |
Sequential Circuit Design | |
Introduction | |
Sequencing Static Circuits | |
Circuit Design of Latches & Flip-Flops | |
Static Sequencing Element Methodology | |
Sequencing Dynamic Circuits | |
Synchronizers | |
Wave Piplining | |
Pitfalls and Fallacies | |
Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies | |
Summary | |
Exercises | |
Design Methodology and Tools | |
Introduction | |
Structured Design Strategies | |
Basic Design Methods | |
Design Flows | |
Behavioral/Functional Synthesis Design Flow (ASIC Design Flow) | |
Programmed Behavioral Synthesis | |
Automated Layout Generation | |
Mixed Signal or Custom Design Flow | |
Additional Design Interchange Formats | |
Design Economics | |
Data Sheets and Documentation | |
Closing the Gap Between ASIC and Custom | |
Historical Perspective | |
Pitfalls and Fallacies | |
Exercises | |
CMOS Physical Design Styles | |
Logic Optimization | |
Testing and Verification | |
Introduction | |
A Walk Through the Test Process | |
Reliability | |
Logic Verification Principles | |
Silicon Debug Principles | |
Manufacturing Test Principles | |
Design for Testability | |
Boundary Scan | |
Pitfalls and Fallacies | |
Historical Perspective | |
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