What is included with this book?
Preface | |
Acknowledgements | |
One Instruction Set Computing | |
What is One Instruction Set Computing? | |
Why Study OISC? | |
A Look Ahead | |
Exercises | |
Instruction Sets | |
Elements of an Instruction | |
Operands | |
Instruction Formats | |
Core Set of Instructions | |
Addressing Modes | |
Exercises | |
Types of Computer Architecture | |
Overview | |
A Simple Taxonomy | |
Accumulator | |
Register-Memory | |
Register-Oriented | |
Exercises | |
Evolution of Instruction Sets | |
Motivation | |
Evolution of Microprocessors | |
Timeline | |
Exercises | |
CISC, RISC, OISC | |
CISC versus RISC | |
Is OISC a CISC or a RISC? | |
Processor Complexity | |
Exercises | |
OISC Architectures | |
Single Instruction Types | |
MOVE | |
Comparing OISC Models | |
Variants of SBN and MOVE | |
OISC Continuum | |
Exercises | |
Historical Review of OISC | |
Subtract and Branch if Negative (SBN) | |
MOVE-Based | |
Timeline | |
Exercises | |
Instruction Set Completeness | |
Instruction Set Completeness | |
A Practical Approach to Determining Completeness | |
Completeness of Two OISCs | |
Exercises | |
OISC Mappings | |
Mapping OISC to Conventional Architectures | |
Synthesizing Instructions | |
Code Fragments | |
Implementing OISC Using OISC | |
Exercises | |
Parallel Architectures | |
Von Neumann Bottleneck | |
Parallel Processing | |
Flynn's Taxonomy for Parallelism | |
Exercises | |
Applications and Implementations | |
OISC-Like Phenomena | |
Field Programmable Gate Arrays | |
Applications | |
Image Processing | |
Future Work with OISC | |
Exercises | |
A Generic Microprocessor and OISC | |
One Instruction Set Computer Implementation | |
Dilation Code Implementation | |
Compiler Output for Dilation | |
OISC Equivalent of Dilation | |
Glossary | |
References | |
Index | |
About the Authors | |
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