Computer Architecture : A Quantitative Approach

by Hennessy; Patterson

• ISBN13: 9781558605961
• ISBN10: 1558605967
• Edition: 3rd
• Format: Hardcover
• Copyright: 2002-05-17
• Publisher: Elsevier Science & Technology

Summary

This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and web technologies, and high performance computing. The book retains its highly rated features: Fallacies and Pitfalls, which share the hard-won lessons of real designers; Historical Perspectives, which provide a deeper look at computer design history; Putting it all Together, which present a design example that illustrates the principles of the chapter; Worked Examples, which challenge the reader to apply the concepts, theories and methods in smaller scale problems; and Cross-Cutting Issues, which show how the ideas covered in one chapter interact with those presented in others. In addition, a new feature, Another View, presents brief design examples in one of the three domains other than the one chosen for Putting It All Together. The authors present a new organization of the material as well, reducing the overlap with their other text, Computer Organization and Design: A Hardware/Software Approach 2/e, and offering more in-depth treatment of advanced topics in multithreading, instruction level parallelism, VLIW architectures, memory hierarchies, storage devices and network technologies. Also new to this edition, is the adoption of the MIPS 64 as the instruction set architecture. In addition to several online appendixes, two new appendixes will be printed in the book: one contains a complete review of the basic concepts of pipelining, the other provides solutions a selection of the exercises. Both will be invaluable to the student or professional learning on her own or in the classroom. Hennessy and Patterson continue to focus on fundamental techniques for designing real machines and for maximizing their cost/performance. * Presents state-of-the-art design examples including: * IA-64 architecture and its first implementation, the Itanium * Pipeline designs for Pentium III and Pentium IV * The cluster that runs the Google search engine * EMC storage systems and their performance * Sony Playstation 2 * Infiniband, a new storage area and system area network * SunFire 6800 multiprocessor server and its processor the UltraSPARC III * Trimedia TM32 media processor and the Transmeta Crusoe processor * Examines quantitative performance analysis in the commercial server market and the embedded market, as well as the traditional desktop market. Updates all the examples and figures with the most recent benchmarks, such as SPEC 2000. * Expands coverage of instruction sets to include descriptions of digital signal processors, media processors, and multimedia extensions to desktop processors. * Analyzes capacity, cost, and performance of disks over two decades. Surveys the role of clusters in scientific computing and commercial computing. * Presents a survey, taxonomy, and the benchmarks of errors and failures in computer systems. * Presents detailed descriptions of the design of storage systems and of clusters. * Surveys memory hierarchies in modern microprocessors and the key parameters of modern disks. * Presents a glossary of networking terms.

Table of Contents

Foreword	vii
Preface	xvii
Acknowledgments	xxv
Fundamentals of Computer Design
Introduction	2	(2)
The Changing Face of Computing and the Task of the Computer Designer	4	(7)
Technology Trends	11	(3)
Cost, Price, and Their Trends	14	(10)
Measuring and Reporting Performance	24	(15)
Quantitative Principles of Computer Design	39	(9)
Putting It All Together: Performance and Price-Performance	48	(8)
Another View: Power Consumption and Efficiency as the Metric	56	(1)
Fallacies and Pitfalls	57	(8)
Concluding Remarks	65	(2)
Historical Perspective and References	67	(23)
Exercises	74	(16)
Instruction Set Principles and Examples
Introduction	90	(2)
Classifying Instruction Set Architectures	92	(3)
Memory Addressing	95	(6)
Addressing Modes for Signal Processing	101	(3)
Type and Size of Operands	104	(1)
Operands for Media and Signal Processing	105	(3)
Operations in the Instruction Set	108	(1)
Operations for Media and Signal Processing	109	(2)
Instructions for Control Flow	111	(6)
Encoding an Instruction Set	117	(3)
Crosscutting Issues: The Role of Compilers	120	(9)
Putting It All Together: The MIPS Architecture	129	(7)
Another View: The Trimedia TM32 CPU	136	(6)
Fallacies and Pitfalls	142	(5)
Concluding Remarks	147	(1)
Historical Perspective and References	148	(24)
Exercises	161	(11)
Instruction-Level Parallelism and Its Dynamic Exploitation
Instruction-Level Parallelism: Concepts and Challenges	172	(9)
Overcoming Data Hazards with Dynamic Scheduling	181	(8)
Dynamic Scheduling: Examples and the Algorithm	189	(7)
Reducing Branch Costs with Dynamic Hardware Prediction	196	(13)
High-Performance Instruction Delivery	209	(6)
Taking Advantage of More ILP with Multiple Issue	215	(9)
Hardware-Based Speculation	224	(16)
Studies of the Limitations of ILP	240	(13)
Limitations on ILP for Realizable Processors	253	(6)
Putting It All Together: The P6 Microarchitecture	259	(13)
Another View: Thread-Level Parallelism	272	(1)
Crosscutting Issues: Using an ILP Data Path to Exploit TLP	273	(1)
Fallacies and Pitfalls	273	(3)
Concluding Remarks	276	(4)
Historical Perspective and References	280	(24)
Exercises	288	(16)
Exploiting Instruction-Level Parallelism with Software Approaches
Basic Compiler Techniques for Exposing ILP	304	(9)
Static Branch Prediction	313	(2)
Static Multiple Issue: The VLIW Approach	315	(4)
Advanced Compiler Support for Exposing and Exploiting ILP	319	(21)
Hardware Support for Exposing More Parallelism at Compile Time	340	(10)
Crosscutting Issues: Hardware versus Software Speculation Mechanisms	350	(1)
Putting It All Together: The Intel IA-64 Architecture and Itanium Processor	351	(12)
Another View: ILP in the Embedded and Mobile Markets	363	(7)
Fallacies and Pitfalls	370	(2)
Concluding Remarks	372	(1)
Historical Perspective and References	373	(17)
Exercises	378	(12)
Memory Hierarchy Design
Introduction	390	(2)
Review of the ABCs of Caches	392	(14)
Cache Performance	406	(7)
Reducing Cache Miss Penalty	413	(10)
Reducing Miss Rate	423	(12)
Reducing Cache Miss Penalty or Miss Rate via Parallelism	435	(8)
Reducing Hit Time	443	(5)
Main Memory and Organizations for Improving Performance	448	(6)
Memory Technology	454	(6)
Virtual Memory	460	(9)
Protection and Examples of Virtual Memory	469	(9)
Crosscutting Issues: The Design of Memory Hierarchies	478	(4)
Putting It All Together: Alpha 21264 Memory Hierarchy	482	(8)
Another View: The Emotion Engine of the Sony Playstation 2	490	(4)
Another View: The Sun Fire 6800 Server	494	(4)
Fallacies and Pitfalls	498	(6)
Concluding Remarks	504	(1)
Historical Perspective and References	504	(24)
Exercises	513	(15)
Multiprocessors and Thread-Level Parallelism
Introduction	528	(12)
Characteristics of Application Domains	540	(9)
Symmetric Shared-Memory Architectures	549	(11)
Performance of Symmetric Shared-Memory Multiprocessors	560	(16)
Distributed Shared-Memory Architectures	576	(8)
Performance of Distributed Shared-Memory Multiprocessors	584	(6)
Synchronization	590	(15)
Models of Memory Consistency: An Introduction	605	(3)
Multithreading: Exploiting Thread-Level Parallelism within a Processor	608	(7)
Crosscutting Issues	615	(7)
Putting It All Together: Sun's Wildfire Prototype	622	(13)
Another View: Multithreading in a Commercial Server	635	(1)
Another View: Embedded Multiprocessors	636	(1)
Fallacies and Pitfalls	637	(6)
Concluding Remarks	643	(6)
Historical Perspective and References	649	(29)
Exercises	665	(13)
Storage Systems
Introduction	678	(1)
Types of Storage Devices	679	(13)
Buses---Connecting I/O Devices to CPU/Memory	692	(10)
Reliability, Availability, and Dependability	702	(3)
RAID: Redundant Arrays of Inexpensive Disks	705	(5)
Errors and Failures in Real Systems	710	(6)
I/O Performance Measures	716	(4)
A Little Queuing Theory	720	(11)
Benchmarks of Storage Performance and Availability	731	(6)
Crosscutting issues	737	(4)
Designing an I/O System in Five Easy Pieces	741	(13)
Putting It All Together: EMC Symmetrix and Celerra	754	(6)
Another View: Sanyo VPC-SX500 Digital Camera	760	(3)
Fallacies and Pitfalls	763	(6)
Concluding Remarks	769	(1)
Historical Perspective and References	770	(18)
Exercises	778	(10)
Interconnection Networks and Clusters
Introduction	788	(5)
A Simple Network	793	(9)
Interconnection Network Media	802	(3)
Connecting More Than Two Computers	805	(9)
Network Topology	814	(7)
Practical Issues for Commercial Interconnection Networks	821	(4)
Examples of Interconnection Networks	825	(5)
Internetworking	830	(4)
Crosscutting Issues for Interconnection Networks	834	(4)
Clusters	838	(5)
Designing a Cluster	843	(12)
Putting It All Together: The Google Cluster of PCs	855	(7)
Another View: Inside a Cell Phone	862	(5)
Fallacies and Pitfalls	867	(3)
Concluding Remarks	870	(1)
Historical Perspective and References	871
Exercises	877
Appendix A Pipelining: Basic and Intermediate Concepts
A.1 Introduction	A-2
A.2 The Major Hurdle of Pipelining-Pipeline Hazards	A-11
A.3 How Is Pipelining Implemented?	A-26
A.4 What Makes Pipelining Hard to Implement?	A-37
A.5 Extending the MIPS Pipeline to Handle Multicycle Operations	A-47
A.6 Putting It All Together: The MIPS R4000 Pipeline	A-57
A.7 Another View: The MIPS R4300 Pipeline	A-66
A.8 Crosscutting Issues	A-67
A.9 Fallacies and Pitfalls	A-77
A.10 Concluding Remarks	A-78
A.11 Historical Perspective and References	A-78
Exercises	A-81
Appendix B Solutions to Selected Exercises
Introduction	B-2
B.1 Chapter 1 Solutions	B-2
B.2 Chapter 2 Solutions	B-7
B.3 Chapter 3 Solutions	B-11
B.4 Chapter 4 Solutions	B-16
B.5 Chapter 5 Solutions	B-21
B.6 Chapter 6 Solutions	B-25
B.7 Chapter 7 Solutions	B-29
B.8 Chapter 8 Solutions	B-30
B.9 Appendix A Solutions	B-35
Online Appendices (www.mkp.com/CA3/)
Appendix C A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
Appendix D An Alternative to RISC: The Intel 80x86
Appendix E Another Alternative to RISC: The VAX Architecture
Appendix F The IBM 360/370 Architecture for Mainframe Computers
Appendix G Vector Processors
Krste Asanovic
Appendix H Computer Arithmetic
David Goldberg
Appendix I Implementing Coherence Protocols
References	R-1
Index	I-1