Computer Systems

by PIMENTEL, ANDY D.; Vassiliadis, Stamatis

• ISBN13: 9783540223771
• ISBN10: 3540223770
• Format: Paperback
• Copyright: 2004-08-31
• Publisher: Springer Verlag

Summary

This book constitutes the refereed proceedings of the 4th International Workshop on Systems, Architectures, Modeling, and Simulation, SAMOS 2004, held in Samos, Greece on July 2004. Besides the SAMOS 2004 proceedings, the book also presents 19 revised papers from the predecessor workshop SAMOS 2003. The 55 revised full papers presented were carefully reviewed and selected for inclusion in the book. The papers are organized in topical sections on reconfigurable computing, architectures and implementation, and systems modeling and simulation.

Table of Contents

SAMOS III -- Reconfigurable Computing
The Molen Programming Paradigm	1	(10)
Stamatis Vassiliadis
Georgi Gaydadjiev
Koen Bertels
Elena Moscu Panainte
Loading ρμ-Code: Design Considerations	11	(9)
Georgi Kuzmanov
Georgi Gaydadjiev
Stamatis Vassiliadis
RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems	20	(10)
Stephane Chevobbe
Nicolas Ventroux
Frederic Blanc
Thierry Collette
Basic OS Support for Distributed Reconfigurable Hardware	30	(9)
Christian Haubelt
Dirk Koch
Jurgen Teich
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications	39	(10)
Jens Peter Wittenburg
Ulrich Schreiber
Ulrich Gries
Markus Schneider
Tim Niggemeier
Customising Processors: Design-Time and Run-Time Opportunities	49	(10)
Wayne Luk
Intermediate Level Components for Reconfigurable Platforms	59	(10)
Erwan Fabiani
Christophe Gouyen
Bernard Pottier
Performance Estimation of Streaming Media Applications for Reconfigurable Platforms	69	(9)
Carsten Reuter
Javier Martin Langerwerf
Hans-Joachim Stolberg
Peter Pirsch
SAMOS III -- Architectures and Implementation
CoDeL: Automatically Synthesizing Network Interface Controllers	78	(10)
Radhakrishnan Sivakumar
Vassilios V. Dimakopulos
Nikitas J. Dimopoulos
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units	88	(10)
Miquel Pericas
Eduard Ayguade
Javier Zalamea
Josep Llosa
Mateo Valero
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs	98	(10)
Ulrich Heinkel
Claus Mayer
Charles Webb
Hans Sahm
Werner Haas
Stefan Gossens
Register-Based Permutation Networks for Stride Permutations	108	(10)
Tuomas Jarvinen
Jarmo Takala
A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures	118	(10)
David Guevorkian
Petri Liuha
Aki Launiainen
Ville Lappalainen
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability	128	(10)
Pascal Benoit
Gilles Sassatelli
Lionel Torres
Didier Demigny
Michel Robert
Gaston Cambon
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs	138	(11)
Tim Kogel
Malte Doerper
Torsten Kempf
Andreas Wieferink
Rainer Leupers
Gerd Ascheid
Heinrich Meyr
SAMOS III -- Compilers, System Modeling, and Simulation
Comparison of Data Dependence Analysis Tests	149	(10)
Miia Viitanen
Timo D. Hamalainen
Mouse: A Shortcut from Matlab Source to SIMD DSP Assembly Code	159	(9)
Gordon Cichon
Gerhard Fettweis
High-Level Energy Estimation for ARM-Based SOCs	168	(10)
Dan Crisu
Sorin Dan Cotofana
Stamatis Vassiliadis
Petri Liuha
IDF Models for Trace Transformations: A Case Study in Computational Refinement	178	(13)
Cagkan Erbas
Simon Polstra
Andy D. Pimentel
Systems, Architectures, Modeling, and Simulation 2004 (SAMOS IV)
Programming Extremely Flexible Platforms	191	(1)
Kees Vissers
SAMOS IV -- Reconfigurable Computing
The Virtex II Pro™ MOLEN Processor	192	(11)
Georgi Kuzmanov
Georgi Gaydadjiev
Stamatis Vassiliadis
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements	203	(10)
Dirk Stroobandt
Hendrik Eeckhaut
Harald Devos
Mark Christiaens
Fabio Verdicchio
Peter Schelkens
Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques	213	(11)
Pedro C. Diniz
Modeling Loop Unrolling: Approaches and Open Issues	224	(10)
Joao M.P. Cardoso
Pedro C. Diniz
Self-loop Pipelining and Reconfigurable Dataflow Arrays	234	(10)
Joao M.P. Cardoso
Architecture Exploration for 3G Telephony Applications Using a Hardware---Software Prototyping Platform	244	(10)
Francois Charot
Madeleine Nyamsi
Patrice Quinton
Charles Wagner
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration	254	(10)
John McAllister
Roger Woods
Richard Walke
On the (Re-)Use of IP-Components in Re-configurable Platforms	264	(10)
Jerome Lemaitre
Sylvain Alliot
Ed Deprettere
Customising Hardware Designs for Elliptic Curve Cryptography	274	(10)
Nicolas Telle
Wayne Luk
Ray C.C. Cheung
Dynamic Hardware Reconfigurations: Performance Impact for MPEG2	284	(9)
Elena Moscu Panainte
Koen Bertels
Stamatis Vassiliadis
Compiler and System Techniques for SoC Distributed Reconfigurable Accelerators	293	(10)
Joel Cambonie
Sylvain Guerin
Ronan Keryell
Loic Lagadec
Bernard Pottier
Olivier Sentieys
Bernt Weber
Samar Yazdani
SAMOS IV -- Architectures and Implementation
Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications	303	(10)
Julio C.B. Mattos
Antonio C.S. Beck
Luigi Carro
Flavio R. Wagner
On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering	313	(10)
Michael Hosemann
Gerhard Fettweis
Memory Bandwidth Requirements of Tile-Based Rendering	323	(10)
Iosif Antochi
Ben Juurlink
Stamatis Vassiliadis
Petri Liuha
Using CoDeL to Rapidly Prototype Network Processsor Extensions	333	(10)
Nainesh Agarwal
Nikitas J. Dimopoulos
Synchronous Transfer Architecture (STA)	343	(10)
Gordon Cichon
Pablo Robelly
Hendrik Seidel
Emil Matus
Marcus Bronzel
Gerhard Fettweis
Generated DSP Cores for Implementation of an OFDM Communication System	353	(10)
Hendrik Seidel
Emil Matus
Gordon Cichon
Pablo Robelly
Marcus Bronzel
Gerhard Fettweis
A Novel Data-Path for Accelerating DSP Kernels	363	(10)
Michalis D. Galanis
G. Theodoridis
Spyros Tragoudas
Dimitrios Soudris
Costas E. Goutis
Scalable FFT Processors and Pipelined Butterfly Units	373	(10)
Jarmo Takala
Konsta Punkka
Scalable Instruction-Level Parallelism	383	(10)
Chris Jesshope
A Low-Power Multithreaded Processor for Baseband Communication Systems	393	(10)
Michael Schulte
John Glossner
Suman Mamidi
Mayan Moudgill
Stamatis Vassiliadis
Initial Evaluation of Multimedia Extensions on VLIW Architectures	403	(10)
Esther Salami
Mateo Valero
HIBI v.2 Communication Network for System-on-Chip	413	(10)
Erno Salminen
Vesa Lahtinen
Tero Kangas
Jouni Riihimaki
Kimmo Kuusilinna
Timo D. Hamalainen
SAMOS IV -- System Modeling, and Simulation
DIF: An Interchange Format for Dataflow-Based Design Tools	423	(10)
Chia-Jui Hsu
Fuat Keceli
Ming-Yung Ko
Shahrooz Shahparnia
Shuvra S. Bhattacharyya
Scalable and Modular Scheduling	433	(10)
Paul Feautrier
Early ISS Integration into Network-on-Chip Designs	443	(10)
Andreas Wieferink
Malte Doerper
Tim Kogel
Rainer Leupers
Gerd Ascheid
Heinrich Meyr
Cycle Accurate Simulation Model Generation for SoC Prototyping	453	(10)
Antoine Fraboulet
Tanguy Risset
Antoine Scherrer
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting	463	(11)
Jianjiang Ceng
Weihua Sheng
Manuel Hohenauer
Rainer Leupers
Gerd Ascheid
Heinrich Meyr
Gunnar Braun
A Communication-Centric Design Flow for HIBI-Based SoCs	474	(10)
Tero Kangas
Jouni Riihimaki
Erno Salminen
Vesa Lahtinen
Heikki Orsila
Kimmo Kuusilinna
Timo D. Hamalainen
Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets	484	(10)
Holger Blume
Thorsten von Sydow
Tobias G. Noll
Communication Optimization in Compaan Process Networks	494	(13)
Ioan Cimpian
Alexandru Turjan
Ed Deprettere
Erwin de Kock
Analysis of Dataflow Programs with Interval-Limited Data-Rates	507	(12)
Jiirgen Teich
Shuvra S. Bhattacharyya
High-Speed Event-Driven RTL Compiled Simulation	519	(11)
Alexey Kupriyanov
Frank Hannig
Jurgen Teich
A High-Level Programming Paradigm for SystemC	530	(10)
Mark Thompson
Andy D. Pimentel
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications	540	(10)
Minas Dasygenis
Erik Brockmeyer
Bart Durinck
Francky Catthoor
Dimitrios Soudris
Antonios Thanailakis
Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration	550	(11)
Laurentiu Nicolae
Ed Deprettere
Author Index	561