Cross-Talk Noise Immune Vlsi Design Using Regular Layout Fabrics

by Khatri, Sunil P.; Brayton, Robert K.; Sangiovanni-Vincentelli, Alberto

• ISBN13: 9780792374077
• ISBN10: 079237407X
• Format: Hardcover
• Copyright: 2001-06-01
• Publisher: Kluwer Academic Pub

Summary

This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems such as cross-talk, electromigration, self-heat, etc. become important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wire. Typical approaches to tackling the cross-talk problem attempt to fix the problem once it is created. This book introduces a framework for cross-talk-free IC design. The main foundation of the book is the use of a predetermined layout pattern on the IC, which we call a 'layout fabric'. The authors characterize this fabric and show how it yields cross-talk-immune designs. Two VLSI design flows are introduced which use the fabric concept. One flow is a minimally modified standard-cell based flow. The other flow uses a network of PLAs to implement the circuit. The authors also introduce 'wire removal' techniques which improve circuit wire ability and thereby reduce circuit area. The new concepts presented here will be of interest to IC designers and researchers.

Table of Contents

List of Figures	p. ix
List of Tables	p. xii
Preface	p. xiii
Acknowledgments	p. xv
Introduction	p. xvii
Introduction	p. 1
Cross-talk in DSM IC Design	p. 1
Book Overview	p. 2
Book Outline	p. 4
Validating Deep Sub-Micron Effects	p. 7
Chapter Overview	p. 7
Trends in DSM VLSI Interconnect	p. 7
Predicting VLSI Process Technology Trends	p. 9
Extracting On-chip Layout Parasitics	p. 10
Capacitance	p. 10
Validating Cross-talk Effects	p. 14
Delay Variation	p. 14
Signal Integrity	p. 16
Review of Existing Techniques	p. 17
Overview	p. 17
Layout-based Techniques	p. 17
Ad-hoc Approaches	p. 17
Custom Layout	p. 18
The DEC Alpha Solution	p. 18
Design CAD based Techniques	p. 19
Post-layout Methods	p. 19
Constraint-driven Methods	p. 19
PLA based Techniques	p. 20
Our Approach	p. 20
Chapter Summary	p. 20
Vlsi Layout Fabrics	p. 23
Chapter Overview	p. 23
Our Dense Wiring Fabric (DWF)	p. 23
Parasitics in the DWF	p. 25
Capacitance	p. 25
Inductance	p. 27
Advantages	p. 28
Delay variation	p. 28
Signal Integrity	p. 31
Power Supply Resistance	p. 33
Uniform and Predictable Inductance	p. 33
Tighter control of t[subscript ins]	p. 34
One-time Parasitic Extraction	p. 34
Applicability of CAD Techniques	p. 34
Routing Flexibility	p. 35
Applicability to Special Circuits	p. 35
Global Clocking	p. 35
Disadvantages	p. 35
Chip Area	p. 36
Total Capacitance	p. 36
Chapter Summary	p. 36
Fabric1 - Fabric Cell Based Design	p. 39
Chapter Overview	p. 39
Design Flow 1	p. 39
Design Methodology	p. 40
Experimental Results	p. 42
Design Flow 2	p. 47
Design Methodology	p. 47
Experimental Results	p. 48
Chapter Summary	p. 51
Fabric3 - Network of Pla Based Design	p. 53
Chapter Overview	p. 53
Programmable Logic Arrays	p. 54
Introduction	p. 55
PLAs in DSM VLSI Design	p. 56
Electrical Characterization	p. 57
Discussion	p. 60
Networks of Programmable Logic Arrays	p. 61
Synthesis Algorithms for the Network of PLAs Methodology	p. 61
Overview	p. 61
Folding Algorithm	p. 62
Results	p. 63
Clustering Algorithm	p. 63
Results	p. 65
Other Clustering Algorithms	p. 66
Design Flow 1	p. 67
Design Methodology	p. 67
Experimental Results	p. 67
Design Flow 2	p. 69
Design Methodology	p. 69
Experimental Results	p. 70
Discussion	p. 73
Cross-talk Problems and our Benchmark Examples	p. 73
Exploring an Alternative to the DWF	p. 74
Inter-Macro Wiring in the DWF	p. 75
Chapter Summary	p. 75
Wire Removal in a Network of Plas	p. 79
Chapter Overview	p. 79
Binary SPFDs	p. 81
Definitions	p. 81
Wire Removal/Replacement Using Binary valued SPFDs	p. 82
MV-SPFDs	p. 82
Definitions	p. 83
Wire Removal/Replacement Using MV-SPFDs	p. 84
Controlling change	p. 86
Multi-valued SPFDs vs binary SPFDs	p. 87
Experimental Results	p. 87
Experiment 1	p. 88
Experiment 2	p. 89
Chapter Summary	p. 93
Conclusions and Future Directions	p. 95
Conclusions	p. 95
Future Work	p. 97
Alternate Fabrics	p. 97
Modifications to the Routing Methodology	p. 98
Modifications to the PLA Design	p. 98
Alternate Circuit Design Styles	p. 99
Reducing Power Consumption	p. 100
Wire Removal	p. 101
Alternative Clustering Strategies	p. 101
"Pre-fabricated" Fabric based Circuits	p. 101
Appendices	p. 107
Standard Cells	p. 107
Index	p. 111
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