Design, Analysis and Test of Logic Circuits Under Uncertainty

by Krishnaswamy, Smita; Markov, Igor L.; Hayes, John P.

• ISBN13: 9789048196432
• ISBN10: 9048196434
• Format: Hardcover
• Copyright: 2012-09-21
• Publisher: Springer Verlag

Summary

Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.

Table of Contents

Introduction	p. 1
Background and Motivation	p. 2
Soft Errors	p. 2
Trends in CMOS	p. 4
Technologies Beyond CMOS	p. 5
Related Work	p. 7
Probabilistic Analysis of Circuits	p. 7
Soft-Error Rate Analysis	p. 8
Fault-Tolerant Design	p. 11
Soft-Error Testing	p. 15
Organization	p. 16
References	p. 17
Probabilistic Transfer Matrices	p. 21
PTM Algebra	p. 22
Basic Operations	p. 23
Additional Operation	p. 26
Handling Correlations	p. 29
Applications	p. 30
Fault Modeling	p. 31
Modeling Glitch Attenuation	p. 31
Error Transfer Functions	p. 35
References	p. 36
Computing with Probabilistic Transfer Matrices	p. 37
Compressing Matrices with Decision Diagrams	p. 37
Computing Circuit PTMs	p. 41
Improving Scalability	p. 45
Dynamic Ordering of Evaluation	p. 45
Hierarchical Reliability Estimation	p. 47
Approximation by Sampling	p. 51
References	p. 52
Testing Logic Circuits for Probabilistic Faults	p. 53
Test-Vector Sensitivity	p. 54
Test Generation	p. 57
References	p. 61
Signature-Based Reliability Analysis	p. 63
SER in Combinational Logic	p. 64
Fault Models for Soft Errors	p. 64
Signatures and Observability Don't-Cares	p. 65
SER Evaluation	p. 68
Multiple-Fault Analysis	p. 70
SER Analysis in Sequential Logic	p. 71
Steady-State and Reachability Analysis	p. 73
Error Persistence and Sequential Observability	p. 74
Additional Masking Mechanisms	p. 76
Incorporating Timing Masking into SER Estimation	p. 76
Electrical Attenuation	p. 80
An Overall SER Evaluation Framework	p. 84
Empirical Validation	p. 85
References	p. 90
Design for Robustness	p. 93
Improving the Reliability of Combinational Logic	p. 93
Signature-Based Design	p. 94
Impact Analysis and Gate Selection	p. 96
Local Logic Rewriting	p. 97
Gate Relocation	p. 98
Improving Sequential Circuit Reliability and Testability	p. 99
Retiming and Sequential SER	p. 100
Retiming and Random-Pattern Testability	p. 103
Retiming by Linear Programs	p. 104
Minimum-Observability Retiming	p. 104
Incorporating Register Sharing	p. 106
Empirical Validation	p. 107
References	p. 113
Summary and Extensions	p. 115
Summary	p. 115
Future Directions	p. 116
Process Variations and Aging Effects	p. 116
Analysis of Biological Systems	p. 117
Concluding Remarks	p. 119
References	p. 120
Index	p. 121
Table of Contents provided by Ingram. All Rights Reserved.