Design for At-Speed Test, Diagnosis and Measurement

by Nadeau-Dostie, Benoit

• ISBN13: 9780792386698
• ISBN10: 0792386698
• Format: Hardcover
• Copyright: 1999-09-01
• Publisher: Kluwer Academic Pub

Summary

Design for AT-Speed Test, Diagnosis and Measurement is the first book to offer practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. Designers will see how the implementation of embedded test enables simplification of silicon debug and system bring-up. Test engineers will determine how embedded test provides a superior level of at-speed test, diagnosis and measurement without exceeding the capabilities of their equipment. Product managers will learn how the time, resources and costs associated with test development, manufacture cost and lifecycle maintenance of their products can be significantly reduced by designing embedded test in the product. A complete design flow and analysis of the impact of embedded test on a design makes this book a 'must read' before any DFT is attempted.

Table of Contents

Table of Contents	v
Foreword	ix
Preface	xv
Technology Overview	1	(34)
Embedded Test	1	(5)
Industry Trends and Conventional Test Methodologies	2	(1)
What is Embedded Test?	3	(1)
icBIST and Embedded Test	4	(2)
DFT Methods Used in Embedded Test	6	(11)
Structural Versus Functional Testing	7	(1)
Built-In Self-Test (BIST)	8	(2)
Test Access Port and Boundary Scan	10	(3)
Scan Design for User Logic	13	(4)
Capabilities of icBIST	17	(16)
icBIST Architectural Framework	18	(1)
At-Speed Logic Test	19	(6)
Embedded Memory Test	25	(2)
Legacy Core Test	27	(1)
Phase-Locked Loop Test	28	(1)
Analog-to-Digital Test	29	(1)
Fault Insertion	29	(1)
External Memory Test	30	(1)
At-Speed Interconnect Test	31	(2)
References	33	(2)
Memory Test and Diagnosis	35	(24)
Overview	35	(1)
Difficulties in Testing Embedded Memories	36	(1)
BIST for Embedded Memories	37	(14)
memBIST-IC Approach	39	(2)
Description of Controllers	41	(4)
BIST Operating Protocol	45	(1)
Embedded Test for Multiple Memories	46	(3)
Creating an Optimal Test Configuration	49	(1)
Reducing Test Time	50	(1)
Reducing Physical Overhead	50	(1)
Increasing Diagnostic Resolution	51	(1)
Diagnosis	51	(6)
Compare Status Pins Approach	52	(1)
Stop-On-Nth-Error Approach	53	(4)
References	57	(2)
Logic Test and Diagnosis	59	(34)
Circuit Preparation	59	(10)
Logic Conventions	59	(1)
General Requirements	60	(1)
Synchronous Circuits	60	(1)
Tri-State Buses	61	(3)
Latches	64	(3)
Non-Scan Flip-Flops	67	(1)
Non-Scannable Blocks	67	(1)
Untestable Logic Gates	68	(1)
Logic BIST Building Blocks	69	(7)
LogicBIST Controller	69	(2)
Scan Chains	71	(1)
Testpoints	72	(4)
Logic Test Configurations and Diagnosis	76	(4)
Logic Test Configurations	76	(3)
Logic BIST Diagnostic Scheme	79	(1)
Scan/ATPG Diagnostic Scheme	80	(1)
Timing Issues and Solutions During Logic Test	80	(12)
logicBIST Controller Clock Sources	81	(1)
Interface for logicBIST Controller and Scan Chains	82	(4)
Scan-Enable Signal Distribution	86	(2)
Interfaces for Flip-Flops in Different Clock Domains	88	(2)
Interfaces to Multi-Cycle Paths	90	(2)
References	92	(1)
Embedded Test Design Flow	93	(24)
Overview of the Design Flow	94	(3)
Adding Embedded Test to Sub-Blocks	95	(1)
Preparing the Top-Level Logic Block	95	(1)
Adding Embedded Test to the Top Level of the Chip	96	(1)
Overview of the Tool Set	97	(2)
Generating Embedded Test	98	(1)
Assembling Embedded Test into the Design	98	(1)
Analyzing the Design with Embedded Test	98	(1)
Verifying the Design with Embedded Test	98	(1)
Required Libraries and Setup	99	(1)
Adding Embedded Test to a Sub-Block	99	(4)
The Sub-Block Flow	99	(1)
Generating Embedded Test for Sub-Blocks	100	(1)
Verifying Embedded Test for Sub-Blocks	101	(2)
Preparing the Top-Level Logic Block	103	(7)
The Logic Flow	103	(1)
Integrating the Sub-Block's Embedded Test	104	(1)
Analyzing the Top-Level Logic Block	105	(1)
Inserting Scan and Testpoints	106	(1)
Reanalyzing the Test-Ready Logic Block	107	(1)
Verifying the Test-Ready Logic Block	108	(2)
Adding Embedded Test to the Top Level of the Chip	110	(7)
Top-Level Flow	111	(1)
Adding Top-Level Embedded Test	112	(1)
Analyzing the Top-Level Embedded Test	113	(1)
Verifying Embedded Test from Chip Pins	114	(3)
Hierarchical Core Test	117	(22)
Testing Cores	117	(4)
Hierarchical SOC Design Process	117	(2)
Embedded Core Test Challenges	119	(1)
Hierarchical Embedded Core Test Architecture	119	(1)
Collar Functions	120	(1)
Collar Generation	121	(1)
Hierarchical Embedded Core Test Solution	121	(3)
Legacy Core Test Hardware	123	(1)
Preparation of Scannable Cores	123	(1)
Embedded Logic Test Architecture	124	(9)
Internal Test Configurations for the Controller	124	(5)
External Test Configuration	129	(1)
Direct Pin Internal Test	130	(1)
Test Collar Elements	131	(2)
Design Flow	133	(3)
Core-Level Design Flow	135	(1)
Chip-Level Design Flow	135	(1)
Summary	136	(1)
References	137	(2)
Test and Measurement for PLLs and ADCs	139	(32)
Testing PLLs	139	(5)
PLL Concepts and Terminology	139	(4)
Function Summary	143	(1)
Measurement Summary	144	(1)
Primary Benefits	144	(1)
Measurements for PLLs	144	(7)
Jitter	145	(3)
Lock Range	148	(1)
Lock Time	149	(1)
Loop Gain	150	(1)
Test Times	151	(1)
Assumptions for Testing PLLs	152	(1)
Testing ADCs	153	(5)
ADC Terminology	153	(3)
Function Summary	156	(1)
Measurement Summary	157	(1)
Primary Benefits	158	(1)
Measurements for ADCs	158	(10)
Best-Fit Polynomial	158	(2)
DNL	160	(1)
Idle Channel Noise	161	(1)
Values of R and C	162	(4)
Values for n (Number of Samples)	166	(1)
Test Times	166	(2)
Assumptions for Testing ADCs	168	(1)
References	169	(2)
System Test and Diagnosis	171	(18)
At-Speed Interconnect Testing	171	(6)
Boundary-Scan Test Strategy	171	(1)
Existing At-Speed Interconnect Test Strategies	172	(1)
New Solution	173	(4)
At-Speed Memory Testing	177	(6)
Conventional Test Approaches	179	(2)
memBIST-XT Features	181	(1)
Memory Test Strategy	182	(1)
Fault Insertion	183	(4)
Fault Insertion Cell Types	184	(1)
Cell Design	184	(3)
Design Flow	187	(1)
References	187	(2)
System Reuse of Embedded Test	189	(28)
Embedded Test	189	(3)
Board and System Embedded Test Primer	192	(1)
Benefits of Using Embedded Test	193	(3)
Benefits for Design Engineering	194	(1)
Benefits for Manufacturing and Failure Analysis	195	(1)
Benefits for Software Groups	195	(1)
General Embedded Test Controller Architecture	196	(5)
The TAP/Embedded Test Controller Interface	196	(2)
Embedded Test Controller Registers	198	(2)
Pattern Generation	200	(1)
Board-Level Test Access	201	(4)
Hardware Requirements	201	(1)
Test Control	202	(1)
Pattern Resequencing	202	(1)
Test Pattern Generation	203	(2)
In-System Card Test Access	205	(5)
Hardware Requirements	205	(3)
Test Control	208	(1)
Pattern Resequencing	209	(1)
Test Pattern Generation	209	(1)
Revision Control	209	(1)
System-Level Test Access	210	(2)
Hardware Requirements	211	(1)
Test Control and Pattern Resequencing	211	(1)
Test Pattern Generation	212	(1)
Sample Embedded Test Flows	212	(4)
LogicVision/ASSET InterTech Flow	212	(2)
LogicVision/Intellitech Flow	214	(2)
References	216	(1)
Glossary	217	(10)
Index	227