Design of Low-Voltage Low-Power Cmos Delta-Sigma A/d Converters

by Peluso, Vincenzo; Steyaert, Michiel; Sansen, Willy M. C.

• ISBN13: 9780792384175
• ISBN10: 0792384172
• Format: Hardcover
• Copyright: 1999-03-01
• Publisher: Kluwer Academic Pub

Summary

Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters investigates the feasibility of designing Delta-Sigma Analog to Digital Converters for very low supply voltage (lower than 1.5V) and low power operation in standard CMOS processes. The chosen technique of implementation is the Switched Opamp Technique which provides Switched Capacitor operation at low supply voltage without the need to apply voltage multipliers or low VtMOST devices. A method of implementing the classic single loop and cascaded Delta-Sigma modulator topologies with half delay integrators is presented. Those topologies are studied in order to find the parameters that maximise the performance in terms of peak SNR. Based on a linear model, the performance degradations of higher order single loop and cascaded modulators, compared to a hypothetical ideal modulator, are quantified. An overview of low voltage Switched Capacitor design techniques, such as the use of voltage multipliers, low VtMOST devices and the Switched Opamp Technique, is given. An in-depth discussion of the present status of the Switched Opamp Technique covers the single-ended Original Switched Opamp Technique, the Modified Switched Opamp Technique, which allows lower supply voltage operation, and differential implementation including common mode control techniques. The restrictions imposed on the analog circuits by low supply voltage operation are investigated. Several low voltage circuit building blocks, some of which are new, are discussed. A new low voltage class AB OTA, especially suited for differential Switched Opamp applications, together with a common mode feedback amplifier and a comparator are presented and analyzed. As part of a systematic top-down design approach, the non-ideal charge transfer of the Switched Opamp integrator cell is modeled, based upon several models of the main opamp non-ideal characteristics. Behavioral simulations carried out with these models yield the required opamp specifications that ensure that the intended performance is met in an implementation. A power consumption analysis is performed. The influence of all design parameters, especially the low power supply voltage, is highlighted. Design guidelines towards low power operation are distilled. Two implementations are presented together with measurement results. The first one is a single-ended implementation of a Delta-Sigma ADC operating with 1.5V supply voltage and consuming 100 mgr;W for a 74 dB dynamic range in a 3.4 kHz bandwidth. The second implementation is differential and operates with 900 mV. It achieves 77 dB dynamic range in 16 kHz bandwidth and consumes 40 mgr;W. Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters is essential reading for analog design engineers and researchers.

Table of Contents

Introduction	1	(6)
Situation of the Research	1	(1)
Overview of Existing Low--Voltage Low--Power ΔΣ A/D Converters	2	(1)
Objectives	3	(1)
Outline	4	(3)
ΔΣ Modulator Topologies	7	(22)
Introduction	7	(1)
Definitions	8	(4)
A Reference ΔΣ Modulator	8	(1)
Performance Criteria	9	(1)
Performance of the Reference ΔΣ Modulator	10	(2)
Single Loop ΔΣ Modulators	12	(7)
Single Loop ΔΣ Modulator using Half Delay Integrators	12	(2)
Single Loop ΔΣ Modulator Performance	14	(3)
Multibit Topologies	17	(2)
Cascaded ΔΣ Modulators	19	(6)
Cascaded Topologies using Half Delay Integrators	19	(2)
Choice of the Parameters	21	(4)
Systematization of the Results	25	(1)
Comparison of Studied Topologies	26	(1)
Conclusions	27	(2)
The Switched Opamp Technique	29	(30)
The Problem of Low Voltage Switched Capacitor Signal Processing	29	(3)
Voltage Multipliers	32	(5)
Existing Voltage Multipliers	32	(1)
The Dickson Multiplier	33	(3)
A Voltage Doubler	36	(1)
Discussion of Voltage Multipliers	37	(1)
Multi Threshold Processes	37	(2)
The Use of Natural Transistors	38	(1)
A Circuit Technique for VT Reduction	38	(1)
Disadvantages of the Use of low VT Transistors	38	(1)
The Switched Opamp Techniques	39	(18)
The Original Switched Opamp Principles	40	(1)
The Key Problem	40	(1)
The Essence of the Switched Opamp Technique	41	(1)
Half Delay Element and Full Delays Switched Opamp Integrator	42	(1)
About Signal Levels	43	(2)
The Modified Switched Opamp Technique	45	(1)
The Principle	45	(2)
The Pitfall	47	(1)
Avoiding the Pitfall	48	(1)
The Egg of Columbus	49	(1)
A Modified Switched Opamp Delay Element	50	(1)
Differential Modified Switched Opamp Technique	50	(1)
Differential Modified Switched Opamp Integrator Cell	50	(2)
Common Mode Feedback Principles	52	(1)
Why Classic Systems Fail	52	(1)
An Error Amplifier Based Approach	52	(1)
An Integrating Control Loop Based approach	53	(1)
An Error Amplifier Based CMFB without Division	53	(2)
Advantages of the Error Amplifier based CMFB	55	(1)
The Switched Opamp Input Problem and Solutions	55	(1)
Using a Physical Resistor at the Input	56	(1)
A Low-Voltage Solution	56	(1)
Conclusion	57	(2)
Low Voltage Circuit Design	59	(40)
Towards Low Supply voltage	59	(5)
Minimal Supply Voltage	59	(2)
Current Mirrors	61	(2)
Cascoding	63	(1)
Analysis of the Low Voltage Current Mirror	64	(2)
A Differential Input Stage	66	(4)
The Differential Input Stage	66	(1)
Frequency Behavior of Hout	67	(3)
Frequency Behavior of H1b	70	(1)
A Class AB OTA	70	(13)
The Topology	71	(1)
DC Transfer Characteristics	72	(1)
A Simple Large Signal Model	72	(3)
Higher Order Model	75	(2)
Frequency Analysis	77	(1)
Transfer Function of Separate Signal Paths	77	(2)
Notes on Setting Behavior	79	(1)
Design Strategy	79	(2)
Noise	81	(2)
CMFB Circuitry	83	(7)
The Trifferential Input Stage	83	(2)
Frequency Analysis	85	(2)
Setting Speed	87	(2)
The Common Mode Sampling Division Factor	89	(1)
Noise	89	(1)
Switching Strategies	90	(5)
Original Method	90	(2)
Fast Switching Method	92	(1)
The Switch Behavior	93	(2)
Comparators	95	(3)
A Regenerative Comparator	95	(1)
Low Voltage Comparator	95	(3)
Conclusions	98	(1)
Design and Power Considerations	99	(26)
Setting Behavior of Integrator	99	(7)
Capacitive Feed Through	100	(1)
Setting process	101	(1)
Finite Gain Effects	102	(1)
Finite Bandwidth	103	(1)
Combined finite gain and bandwidth	104	(2)
Functionality of CMFB	106	(2)
Optimization of the Operating Point	108	(1)
Linear Setting	108	(1)
Linear Setting with Slewing	108	(1)
Strong inversion	109	(1)
Weak Inversion	109	(1)
Comparison	109	(1)
Noise	109	(7)
Circuit Noise Contributions in an ΔΣ modulator	110	(1)
Suppression of Noise Generated Inside the Loop	111	(3)
Noise Trade-off	114	(2)
Power Considerations	116	(7)
Switched Capacitor integrator power consumption	116	(3)
Discussion of Elements Influencing Power Consumption	119	(4)
Conclusions	123	(2)
Implementations	125	(16)
A 1.5 V - 100μW ΔΣ Modulator	125	(1)
The Architecture	125	(1)
Measurement Results	126	(1)
A 900mV - 40μW ΔΣ Modulator	126	(15)
Architecture	128	(5)
Measurement Setup	133	(3)
Measurement Results	136	(1)
Conclusions	136	(5)
Final Discussion	141	(3)
Conclusions	141	(1)
Possibilities for Future Work	142	(2)
Appendices	144	(19)
A-- Calculations for Chapter 3	145	(8)
A.1 Efficiency Calculation of the Dickson Multiplier	145	(3)
A.2 Calculation of the required CCM	148	(1)
A.3 Calculation of the required CCM, aux	149	(1)
A.4 Calculation of the Modified Switched Opamp Integrator Transfer Function	150	(3)
B-- Calculation for Chapter 4	153	(4)
B.1 Noise Analysis of Low Voltage Current Mirror	153	(1)
B.2 Noise Analysis of New Input Stage	154	(1)
B.3 Derivation of Trifferential Stage Branch Currents	155	(2)
C-- Setting Analysis	157	(6)
C.1 Pole-Zero Pair with Frequency Lower than Gain-Bandwidth	157	(1)
C.2 Pole-Zero Pair with Frequency higher than Gain-Bandwidth	158	(1)
C.3 Pole-Zero Doublet at Frequency higher than Gain-Bandwidth	159	(1)
C.4 Two Complex Poles and a Zero	159	(2)
C.5 General Conclusions	161	(2)
References	163	(10)
Index	173