Designing Digital Computer Systems with Verilog

by David J. Lilja , Sachin S. Sapatnekar

• ISBN13: 9780521828666
• ISBN10: 052182866X
• Format: Hardcover
• Copyright: 2005-01-17
• Publisher: Cambridge University Press

Summary

This unique book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioral and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers.

Author Biography

David J. Lilja received his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign Sachin S. Sapatnekar received his Ph.D from the University of Illinois at Urbana-Champaign

Table of Contents

Preface	vii
1 Controlling complexity	1	(6)
1.1 Hierarchical design flow	1	(3)
1.2 Designing hardware with software	4	(2)
1.3 Summary	6	(1)
2 A Verilogical place to start	7	(25)
2.1 My Veri first description	7	(2)
2.2 A more formal introduction to the basics	9	(7)
2.3 Behavioral and structural models	16	(12)
2.4 Functions and tasks	28	(2)
2.5 Summary	30	(1)
Further reading	31	(1)
3 Defining the instruction set architecture	32	(26)
3.1 Instruction set design	32	(3)
3.2 Defining the VeSPA instruction set	35	(13)
3.3 Specifying the VeSPA ISA	48	(8)
3.4 Summary	56	(1)
Further reading	56	(2)
4 Algorithmic behavioral modeling	58	(24)
4.1 Module definition	59	(1)
4.2 Instruction and storage element definitions	59	(5)
4.3 Fetch-execute loop	64	(4)
4.4 Fetch task	68	(3)
4.5 Execute task	71	(6)
4.6 Condition code tasks	77	(2)
4.7 Tracing instruction execution	79	(2)
4.8 Summary	81	(1)
5 Building an assembler for VeSPA	82	(12)
5.1 Why assembly language?	82	(1)
5.2 The assembly process	83	(5)
5.3 VASM - the VeSPA assembler	88	(4)
5.4 Linking and loading	92	(1)
5.5 Summary	92	(2)
6 Pipelining	94	(11)
6.1 Instruction partitioning for pipelining	94	(2)
6.2 Pipeline performance	96	(1)
6.3 Dependences and hazards	97	(6)
6.4 Dealing with pipeline hazards	103	(1)
6.5 Summary	104	(1)
Further reading	104	(1)
7 Implementation of the pipelined processor	105	(13)
7.1 Pipelining VeSPA	105	(1)
7.2 The hazard detection unit	106	(2)
7.3 Overview of the pipeline structure	108	(1)
7.4 A detailed description of the pipeline stages	109	(6)
7.5 Timing considerations	115	(2)
7.6 Summary	117	(1)
Further reading	117	(1)
8 Verification	118	(14)
8.1 Component-level test benches	118	(9)
8.2 System-level self-testing	127	(3)
8.3 Formal verification	130	(1)
8.4 Summary	131	(1)
Further reading	131	(1)
A The VeSPA instruction set architecture (ISA)	132	(15)
A.1 Notational conventions	132	(1)
A.2 Storage elements	133	(1)
A.3 The instruction specifications	133	(14)
B The VASM assembler	147	(6)
B.1 Notational conventions	147	(1)
B.2 Assembler directives	148	(1)
B.3 Example program	149	(1)
B.4 Modifying the assembler	149	(3)
Further reading	152	(1)
Index	153