Digital Design

by Wakerly, John F.

• ISBN13: 9780137691913
• ISBN10: 0137691912
• Edition: 3rd
• Format: Hardcover
• Copyright: 1999-08-01
• Publisher: PRENTICE HALL

Summary

Foundation Title. This newly revised text blends academic precision and practical experience in an authoritative introduction to basic principles of digital design and practical requirements in both board-level and VLSI systems. The text covers the fundamental building blocks of digital design across several levels of abstraction, from CMOS gates to hardware design languages. Packaged with XILINX Student Edition.

Table of Contents

Foreword	xv
Preface	xvii
Introduction	1	(24)
About Digital Design	1	(2)
Analog versus Digital	3	(3)
Digital Devices	6	(1)
Electronic Aspects of Digital Design	7	(2)
Software Aspects of Digital Design	9	(3)
Integrated Circuits	12	(3)
Programmable Logic Devices	15	(1)
Application-Specific ICs	16	(2)
Printed-Circuit Boards	18	(1)
Digital-Design Levels	18	(4)
The Name of the Game	22	(1)
Going Forward	23	(2)
Drill Problems	24	(1)
Number Systems And Codes	25	(54)
Positional Number Systems	26	(1)
Octal and Hexadecimal Numbers	27	(2)
General Positional-Number-System Conversions	29	(3)
Addition and Subtraction of Nondecimal Numbers	32	(2)
Representation of Negative Numbers	34	(5)
Signed-Magnitude Representation
Complement Number Systems
Radix-Complement Representation
Two's-Complement Representation
Diminished Radix-Complement Representation
Ones'-Complement Representation
Excess Representations
Two's-Complement Addition and Subtraction	39	(5)
Addition Rules
A Graphical View
Overflow
Subtraction Rules
Two's-Complement and Unsigned Binary Numbers
Ones'-Complement Addition and Subtraction	44	(1)
Binary Multiplication	45	(2)
Binary Division	47	(1)
Binary Codes for Decimal Numbers	48	(3)
Gray Code	51	(2)
Character Codes	53	(1)
Codes for Actions, Conditions, and States	53	(4)
n-Cubes and Distance	57	(1)
Codes for Detecting and Correcting Errors	58	(11)
Error-Detecting Codes
Error-Correcting and Multiple-Error-Detecting Codes
Hamming Codes
CRC Codes
Two-Dimensional Codes
Checksum Codes
m-out-of-n Codes
Codes for Serial Data Transmission and Storage	69	(10)
Parallel and Serial Data
Serial Line Codes
References	73	(1)
Drill Problems	74	(2)
Exercises	76	(3)
Digital Circuits	79	(114)
Logic Signals and Gates	80	(4)
Logic Families	84	(2)
CMOS Logic	86	(10)
CMOS Logic Levels
MOS Transistors
Basic CMOS Inverter Circuit
CMOS NAND and NOR Gates
Fan-In
Noninverting Gates
CMOS AND-OR-INVERT and OR-AND-INVERT Gates
Electrical Behavior of CMOS Circuits	96	(3)
Overview
Data Sheets and Specifications
CMOS Steady-State Electrical Behavior	99	(14)
Logic Levels and Noise Margins
Circuit Behavior with Resistive Loads
Circuit Behavior with Nonideal Inputs
Fanout
Effects of Loading
Unused Inputs
Current Spikes and Decoupling Capacitors
How to Destroy a CMOS Device
CMOS Dynamic Electrical Behavior	113	(10)
Transition Time
Propagation Delay
Power Consumption
Other CMOS Input and Output Structures	123	(12)
Transmission Gates
Schmitt-Trigger Inputs
Three-State Outputs
Open-Drain Outputs
Driving LEDs
Multisource Buses
Wired Logic
Pull-Up Resistors
CMOS Logic Families	135	(10)
HC and HCT
VHC and VHCT
HC, HCT, VHC, and VHCT Electrical Characteristics
FCT and FCT-T
FCT-T Electrical Characteristics
Bipolar Logic	145	(11)
Diodes
Diode Logic
Bipolar Junction Transistors
Transistor Logic Inverter
Schottky Transistors
Transistor-Transistor Logic	156	(10)
Basic TTL NAND Gate
Logic Levels and Noise Margins
Fanout
Unused Inputs
Additional TTL Gate Types
TTL Families	166	(4)
Early TTL Families
Schottky TTL Families
Characteristics of TTL Families
A TTL Data Sheet
CMOS/TTL Interfacing	170	(1)
Low-Voltage CMOS Logic and Interfacing	171	(4)
3.3-V LVTTL and LVCMOS Logic
5-V Tolerant Inputs
5-V Tolerant Outputs
TTL/LVTTL Interfacing Summary
2.5-V and 1.8-V Logic
Emitter-Coupled Logic	175	(18)
Basic CML Circuit
ECL 10K/10H Families
ECL 100K Family
Positive ECL (PECL)
References	183	(1)
Drill Problems	184	(4)
Exercises	188	(5)
Combinational Logic Design Principles	193	(118)
Switching Algebra	194	(15)
Axioms
Single-Variable Theorems
Two- and Three-Variable Theorems
n-Variable Theorems
Duality
Standard Representations of Logic Functions
Combinational-Circuit Analysis	209	(6)
Combinational-Circuit Synthesis	215	(21)
Circuit Descriptions and Designs
Circuit Manipulations
Combinational-Circuit Minimization
Karnaugh Maps
Minimizing Sums of Products
Simplifying Products of Sums
``Don't-Care'' Input Combinations
Multiple-Output Minimization
Programmed Minimization Methods	236	(8)
Representation of Product Terms
Finding Prime Implicants by Combining Product Terms
Finding a Minimal Cover Using a Prime-Implicant Table
Other Minimization Methods
Timing Hazards	244	(5)
Static Hazards
Finding Static Hazards Using Maps
Dynamic Hazards
Designing Hazard-Free Circuits
The ABEL Hardware Description Language	249	(15)
ABEL Program Structure
ABEL Compiler Operation
WHEN Statements and Equation Blocks
Truth Tables
Ranges, Sets, and Relations
Don't-Care Inputs
Test Vectors
The VHDL Hardware Description Language	264	(47)
Design Flow
Program Structure
Types and Constants
Functions and Procedures
Libraries and Packages
Structural Design Elements
Dataflow Design Elements
Behavioral Design Elements
The Time Dimension and Simulation
Synthesis
References	298	(3)
Drill Problems	301	(3)
Exercises	304	(7)
Combinational Logic Design Practices	311	(156)
Documentation Standards	312	(18)
Block Diagrams
Gate Symbols
Signal Names and Active Levels
Active Levels for Pins
Bubble-to-Bubble Logic Design
Drawing Layout
Buses
Additional Schematic Information
Circuit Timing	330	(7)
Timing Diagrams
Propagation Delay
Timing Specifications
Timing Analysis
Timing Analysis Tools
Combinational PLDs	337	(14)
Programmable Logic Arrays
Programmable Array Logic Devices
Generic Array Logic Devices
Bipolar PLD Circuits
CMOS PLD Circuits
Device Programming and Testing
Decoders	351	(25)
Binary Decoders
Logic Symbols for Larger-Scale Elements
The 74x139 Dual 2-to-4 Decoder
The 74x138 3-to-8 Decoder
Cascading Binary Decoders
Decoders in ABEL and PLDs
Decoders in VHDL
Seven-Segment Decoders
Encoders	376	(9)
Priority Encoders
The 74x148 Priority Encoder
Encoders in ABEL and PLDs
Encoders in VHDL
Three-State Devices	385	(13)
Three-State Buffers
Standard SSI and MSI Three-State Buffers
Three-State Outputs in ABEL and PLDs
Three-State Outputs in VHDL
Multiplexers	398	(12)
Standard MSI Multiplexers
Expanding Multiplexers
Multiplexers, Demultiplexers, and Buses
Multiplexers in ABEL and PLDs
Multiplexers in VHDL
Exclusive-OR Gates and Parity Circuits	410	(9)
Exclusive-OR and Exclusive-NOR Gates
Parity Circuits
The 74x280 9-Bit Parity Generator
Parity-Checking Applications
Exclusive-OR Gates and Parity Circuits in ABEL and PLDs
Exclusive-OR Gates and Parity Circuits in VHDL
Comparators	419	(11)
Comparator Structure
Iterative Circuits
An Iterative Comparator Circuit
Standard MSI Comparators
Comparators in ABEL and PLDs
Comparators in VHDL
Adders, Subtractors, and ALUs	430	(16)
Half Adders and Full Adders
Ripple Adders
Subtractors
Carry Lookahead Adders
MSI Adders
MSI Arithmetic and Logic Units
Group-Carry Lookahead
Adders in ABEL and PLDs
Adders in VHDL
Combinational Multipliers	446	(21)
Combinational Multiplier Structures
Multiplication in ABEL and PLDs
Multiplication in VHDL
References	455	(1)
Drill Problems	456	(3)
Exercises	459	(8)
Combinational-Circuit Design Examples	467	(62)
Building-Block Design Examples	468	(11)
Barrel Shifter
Simple Floating-Point Encoder
Dual-Priority Encoder
Cascading Comparators
Mode-Dependent Comparator
Design Examples Using ABEL and PLDs	479	(21)
Barrel Shifter
Simple Floating-Point Encoder
Dual-Priority Encoder
Cascading Comparators
Mode-Dependent Comparator
Ones Counter
Tic-Tac-Toe
Design Examples Using VHDL	500	(29)
Barrel Shifter
Simple Floating-Point Encoder
Dual-Priority Encoder
Cascading Comparators
Mode-Dependent Comparator
Ones Counter
Tic-Tac-Toe
Exercises	527	(2)
Sequential Logic Design Principles	529	(130)
Bistable Elements	531	(3)
Digital Analysis
Analog Analysis
Metastable Behavior
Latches and Flip-Flops	534	(16)
S-R Latch
S-R Latch
S-R Latch with Enable
D Latch
Edge-Triggered D Flip-Flop
Edge-Triggered D Flip-Flop with Enable
Scan Flip-Flop
Master/Slave S-R Flip-Flop
Master/Slave J-K Flip-Flop
Edge-Triggered J-K Flip-Flop
T Flip-Flop
Clocked Synchronous State-Machine Analysis	550	(13)
State-Machine Structure
Output Logic
Characteristic Equations
Analysis of State Machines with D Flip-Flops
Analysis of State Machines with J-K Flip-Flops
Clocked Synchronous State-Machine Design	563	(21)
State-Table Design Example
State Minimization
State Assignment
Synthesis Using D Flip-Flops
Synthesis Using J-K Flip-Flops
More Design Examples Using D Flip-Flops
Designing State Machines Using State Diagrams	584	(7)
State-Machine Synthesis Using Transition Lists	591	(3)
Transition Equations
Excitation Equations
Variations on the Scheme
Realizing the State Machine
Another State-Machine Design Example	594	(8)
The Guessing Game
Unused States
Output-Coded State Assignment
``Don't-Care'' State Codings
Decomposing State Machines	602	(2)
Feedback Sequential Circuits	604	(11)
Analysis
Analyzing Circuits with Multiple Feedback Loops
Races
State Tables and Flow Tables
CMOS D Flip-Flop Analysis
Feedback Sequential-Circuit Design	615	(12)
Latches
Designing Fundamental-Mode Flow Table
Flow-Table Minimization
Race-Free State Assignment
Excitation Equations
Essential Hazards
Summary
ABEL Sequential-Circuit Design Features	627	(14)
Registered Outputs
State Diagrams
External State Memory
Specifying Moore Outputs
Specifying Mealy and Pipelined Outputs with WITH
Test Vectors
VHDL Sequential-Circuit Design Features	641	(18)
Feedback Sequential Circuits
Clocked Circuits
References	644	(2)
Drill Problems	646	(4)
Exercises	650	(9)
Sequential Logic Design Practices	659	(136)
Sequential-Circuit Documentation Standards	660	(6)
General Requirements
Logic Symbols
State-Machine Descriptions
Timing Diagrams and Specifications
Latches and Flip-Flops	666	(15)
SSI Latches and Flip-Flops
Switch Debouncing
The Simplest Switch Debouncer
Bus Holder Circuit
Multibit Registers and Latches
Registers and Latches in ABEL and PLDs
Registers and Latches in VHDL
Sequential PLDs	681	(12)
Bipolar Sequential PLDs
Sequential GAL Devices
PLD Timing Specifications
Counters	693	(19)
Ripple Counters
Synchronous Counters
MSI Counters and Applications
Decoding Binary-Counter States
Counters in ABEL and PLDs
Counters in VHDL
Shift Registers	712	(35)
Shift-Register Structure
MSI Shift Registers
The World's Biggest Shift-Register Application
Serial/Parallel Conversion
Shift-Register Counters
Ring Counters
Johnson Counters
Linear Feedback Shift-Register Counters
Shift Registers in ABEL and PLDs
Shift Registers in VHDL
Iterative versus Sequential Circuits	747	(3)
Synchronous Design Methodology	750	(7)
Synchronous System Structure
A Synchronous System Design Example
Impediments to Synchronous Design	757	(7)
Clock Skew
Gating the Clock
Asynchronous Inputs
Synchronizer Failure and Metastability	764	(31)
Synchronizer Failure
Metastability Resolution Time
Reliable Synchronizer Design
Analysis of Metastable Timing
Better Synchronizers
Other Synchronizer Designs
Metastable-Hardened Flip-Flops
Synchronizing High-Speed Data Transfers
References	784	(2)
Drill Problems	786	(2)
Exercises	788	(7)
Sequential-Circuit Design Examples	795	(36)
Design Examples Using ABEL and PLDs	796	(17)
Timing and Packaging of PLD-Based State Machines
A Few Simple Machines
T-Bird Tail Lights
The Guessing Game
Reinventing Traffic-Light Controllers
Design Examples Using VHDL	813	(18)
A Few Simple Machines
T-Bird Tail Lights
The Guessing Game
Reinventing Traffic-Light Controllers
Exercises	829	(2)
Memory, CPLDS, And FPGAS	831	(64)
Read-Only Memory	832	(22)
Using ROMs for ``Random'' Combinational Logic Functions
Internal ROM Structure
Two-Dimensional Decoding
Commercial ROM Types
ROM Control Inputs and Timing
ROM Applications
Read/Write Memory	854	(1)
Static RAM	854	(12)
Static-RAM Inputs and Outputs
Static-RAM Internal Structure
Static-RAM Timing
Standard Static RAMs
Synchronous SRAM
Dynamic RAM	866	(6)
Dynamic-RAM Structure
Dynamic-RAM Timing
Synchronous DRAMs
Complex Programmable Logic Devices	872	(10)
Xilinx XC9500 CPLD Family
Function-Block Architecture
Input/Output-Block Architecture
Switch Matrix
Field-Programmable Gate Arrays	882	(13)
Xilinx XC4000 FPGA Family
Configurable Logic Block
Input/Output Block
Programmable Interconnect
References	891	(1)
Drill Problems	892	(1)
Exercises	892	(3)
Additional Real-World Topics	895	(28)
Computer-Aided Design Tools	895	(7)
Hardware Description Languages
Schematic Capture
Timing Drawings and Specifications
Circuit Analysis and Simulation PCB Layout
Design for Testability	902	(6)
Testing
Bed-of-Nails and In-Circuit Testing
Scan Methods
Estimating Digital System Reliability	908	(4)
Failure Rates
Reliability and MTBF
System Reliability
Transmission Lines, Reflections, and Termination	912	(11)
Basic Transmission-Line Theory
Logic-Signal Interconnections as Transmission Lines
Logic-Signal Terminations
References	920	(3)
Index	923