Digital Design and Computer Architecture

by Harris; Harris

• ISBN13: 9780123704979
• ISBN10: 0123704979
• eBook ISBN(s): 9780080547060
• Format: Paperback
• Copyright: 2007-03-02
• Publisher: Elsevier Science
• More Book Details
• Purchase Benefits

Summary

Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of Digital Design and Computer Architecture, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works--even if they have no formal background in design or architecture beyond an introductory class. David Harris and Sarah Harris combine an engaging and humorous writing style with an updated and hands-on approach to digital design. Unique presentation of digital logic design from the perspective of computer architecture using a real instruction set, MIPS. Side-by-side examples of the two most prominent Hardware Design Languages--VHDL and Verilog--illustrate and compare the ways the each can be used in the design of digital systems. Worked examples conclude each section to enhance the reader's understanding and retention of the material. Companion Web site includes links to CAD tools for FPGA design from Synplicity and Xilinx, lecture slides, laboratory projects, and solutions to exercises.

Author Biography

Sarah L. Harris is an assistant professor of engineering at Harvey Mudd College.

Table of Contents

Preface	p. xvii
Features	p. xviii
Online Supplements	p. xix
How to Use the Software Tools in a Course	p. xix
Labs	p. xx
Bugs	p. xxi
Acknowledgments	p. xxi
From Zero to One	p. 3
The Game Plan	p. 3
The Art of Managing Complexity	p. 4
Abstraction	p. 4
Discipline	p. 5
The Three -Y's	p. 6
The Digital Abstraction	p. 7
Number Systems	p. 9
Decimal Numbers	p. 9
Binary Numbers	p. 9
Hexadecimal Numbers	p. 11
Bytes, Nibbles, and All That Jazz	p. 13
Binary Addition	p. 14
Signed Binary Numbers	p. 15
Logic Gates	p. 19
NOT Gate	p. 20
Buffer	p. 20
AND Gate	p. 20
OR Gate	p. 21
Other Two-Input Gates	p. 21
Multiple-Input Gates	p. 21
Beneath the Digital Abstraction	p. 22
Supply Voltage	p. 22
Logic Levels	p. 22
Noise Margins	p. 23
DC Transfer Characteristics	p. 23
The Static Discipline	p. 24
CMOS Transistors	p. 26
Semiconductors	p. 27
Diodes	p. 27
Capacitors	p. 28
nMOS and pMOS Transistors	p. 28
CMOS NOT Gate	p. 31
Other CMOS Logic Gates	p. 31
Transmission Gates	p. 33
Pseudo-nMOS Logic	p. 33
Power Consumption	p. 34
Summary and a Look Ahead	p. 35
Exercises	p. 37
Interview Questions	p. 48
Combinational Logic Design	p. 51
Introduction	p. 51
Boolean Equations	p. 54
Terminology	p. 54
Sum-of-Products Form	p. 54
Product-of-Sums Form	p. 56
Boolean Algebra	p. 56
Axioms	p. 57
Theorems of One Variable	p. 57
Theorems of Several Variables	p. 58
The Truth Behind It All	p. 60
Simplifying Equations	p. 61
From Logic to Gates	p. 62
Multilevel Combinational Logic	p. 65
Hardware Reduction	p. 66
Bubble Pushing	p. 67
X's and Z's, Oh My	p. 69
Illegal Value: X	p. 69
Floating Value: Z	p. 70
Karnaugh Maps	p. 71
Circular Thinking	p. 73
Logic Minimization with K-Maps	p. 73
Don't Cares	p. 77
The Big Picture	p. 78
Combinational Building Blocks	p. 79
Multiplexers	p. 79
Decoders	p. 82
Timing	p. 84
Propagation and Contamination Delay	p. 84
Glitches	p. 88
Summary	p. 91
Exercises	p. 93
Interview Questions	p. 100
Sequential Logic Design	p. 103
Introduction	p. 103
Latches and Flip-Flops	p. 103
SR Latch	p. 105
D Latch	p. 107
D Flip-Plop	p. 108
Register	p. 108
Enabled Flip-Flop	p. 109
Resettable Flip-Flop	p. 110
Transistor-Level Latch and Flip-Flop Designs	p. 110
Putting It All Together	p. 112
Synchronous Logic Design	p. 113
Some Problematic Circuits	p. 113
Synchronous Sequential Circuits	p. 114
Synchronous and Asynchronous Circuits	p. 116
Finite State Machines	p. 117
FSM Design Example	p. 117
State Encodings	p. 123
Moore and Mealy Machines	p. 126
Factoring State Machines	p. 129
FSM Review	p. 132
Timing of Sequential Logic	p. 133
The Dynamic Discipline	p. 134
System Tinting	p. 135
Clock Skew	p. 140
Metastability	p. 143
Synchronizers	p. 144
Derivation of Resolution Time	p. 146
Parallelism	p. 149
Summary	p. 153
Exercises	p. 155
Interview Questions	p. 165
Hardware Description Languages	p. 167
Introduction	p. 167
Modules	p. 167
Language Origins	p. 168
Simulation and Synthesis	p. 169
Combinational Logic	p. 171
Bitwise Operators	p. 171
Comments and White Space	p. 174
Reduction Operators	p. 174
Conditional Assignment	p. 175
Internal Variables	p. 176
Precedence	p. 178
Numbers	p. 179
Z's and X's	p. 179
Bit Swizzling	p. 182
Delays	p. 182
VHDL Libraries and Types	p. 183
Structural Modeling	p. 185
Sequential Logic	p. 190
Registers	p. 190
Resettable Registers	p. 191
Enabled Registers	p. 193
Multiple Registers	p. 194
Latches	p. 195
More Combinational Logic	p. 195
Case Statements	p. 198
If Statements	p. 199
Verilog casez	p. 201
Blocking and Nonblocking Assignments	p. 201
Finite State Machines	p. 206
Parameterized Modules	p. 211
Testbenches	p. 214
Summary	p. 218
Exercises	p. 219
Interview Questions	p. 230
Digital Building Blocks	p. 233
Introduction	p. 233
Arithmetic Circuits	p. 233
Addition	p. 233
Subtraction	p. 240
Comparators	p. 240
ALU	p. 242
Shifters and Rotators	p. 244
Multiplication	p. 246
Division	p. 247
Further Reading	p. 248
Number Systems	p. 249
Fixed-Point Number Systems	p. 249
Floating-Point Number Systems	p. 250
Sequential Building Blocks	p. 254
Counters	p. 254
Shift Registers	p. 255
Memory Arrays	p. 257
Overview	p. 257
Dynamic Random Access Memory	p. 260
Static Random Access Memory	p. 260
Area and Delay	p. 261
Register Files	p. 261
Read Only Memory	p. 262
Logic Using Memory Arrays	p. 264
Memory HDL	p. 264
Logic Arrays	p. 266
Programmable Logic Array	p. 266
Field Programmable Gate Array	p. 268
Array Implementations	p. 273
Summary	p. 274
Exercises	p. 276
Interview Questions	p. 286
Architecture	p. 289
Introduction	p. 289
Assembly Language	p. 290
Instructions	p. 290
Operands: Registers, Memory, and Constants	p. 292
Machine Language	p. 299
R-type Instructions	p. 299
I-type Instructions	p. 301
J-type Instructions	p. 302
Interpreting Machine Language Code	p. 302
The Power of the Stored Program	p. 303
Programming	p. 304
Arithmetic/Logical Instructions	p. 304
Branching	p. 308
Conditional Statements	p. 310
Getting Loopy	p. 311
Arrays	p. 314
Procedure Calls	p. 319
Addressing Modes	p. 327
Lights, Camera, Action: Compiling, Assembling, and Loading	p. 330
The Memory Map	p. 330
Translating and Starting a Program	p. 331
Odds and Ends	p. 336
Pseudoinstructions	p. 336
Exceptions	p. 337
Signed and Unsigned Instructions	p. 338
Floating-Point Instructions	p. 340
Real-World Perspective: IA-32 Architecture	p. 341
IA-32 Registers	p. 342
IA-32 Operands	p. 342
Status Flags	p. 344
IA-32 Instructions	p. 344
IA-32 Instruction Encoding	p. 346
Other IA-32 Peculiarities	p. 348
The Big Picture	p. 349
Summary	p. 349
Exercises	p. 351
Interview Questions	p. 361
Microarchitecture	p. 363
Introduction	p. 363
Architectural State and Instruction Set	p. 363
Design Process	p. 364
MIPS Microarchitectures	p. 366
Performance Analysis	p. 366
Single-Cycle Processor	p. 368
Single-Cycle Datapath	p. 368
Single-Cycle Control	p. 374
More Instructions	p. 377
Performance Analysis	p. 380
Multicycle Processor	p. 381
Multicycle Datapath	p. 382
Multicycle Control	p. 388
More Instructions	p. 395
Performance Analysis	p. 397
Pipelined Processor	p. 401
Pipelined Datapath	p. 404
Pipelined Control	p. 405
Hazards	p. 406
More Instructions	p. 418
Performance Analysis	p. 418
HDL Representation	p. 421
Single-Cycle Processor	p. 422
Generic Building Blocks	p. 426
Testbench	p. 428
Exceptions	p. 431
Advanced Microarchitecture	p. 435
Deep Pipelines	p. 435
Branch Prediction	p. 437
Superscalar Processor	p. 438
Out-of-Order Processor	p. 441
Register Renaming	p. 443
Single Instruction Multiple Data	p. 445
Multithreading	p. 446
Multiprocessors	p. 447
Real-World Perspective: IA-32 Microarchitecture	p. 447
Summary	p. 453
Exercises	p. 455
Interview Questions	p. 461
Memory Systems	p. 463
Introduction	p. 463
Memory System Performance Analysis	p. 467
Caches	p. 468
What Data Is Held in the Cache?	p. 469
How Is the Data Found?	p. 470
What Data Is Replaced?	p. 478
Advanced Cache Design	p. 479
The Evolution of MIPS Caches	p. 483
Virtual Memory	p. 484
Address Translation	p. 486
The Page Table	p. 488
The Translation Lookaside Buffer	p. 490
Memory Protection	p. 491
Replacement Policies	p. 492
Multilevel Page Tables	p. 492
Memory-Mapped I/O	p. 494
Real-World Perspective: IA-32 Memory and I/O Systems	p. 499
IA-32 Cache Systems	p. 499
IA-32 Virtual Memory	p. 501
IA-32 Programmed I/O	p. 502
Summary	p. 502
Exercises	p. 504
Interview Questions	p. 512
Digital System Implementation	p. 515
Introduction	p. 515
74xx Logic	p. 515
Logic Gates	p. 516
Other Functions	p. 516
Programmable Logic	p. 516
PROMs	p. 516
PLAs	p. 520
FPGAs	p. 521
Application-Specific Integrated Circuits	p. 523
Data Sheets	p. 523
Logic Families	p. 529
Packaging and Assembly	p. 531
Transmission lines	p. 534
Matched Termination	p. 536
Open Termination	p. 538
Short Termination	p. 539
Mismatched Termination	p. 539
When to Use Transmission Line Models	p. 542
Proper Transmission Line Terminations	p. 542
Derivation of Z[subscript 0]	p. 544
Derivation of the Reflection Coefficient	p. 545
Putting It All Together	p. 546
Economics	p. 547
MIPS Instructions	p. 551
Further Reading	p. 555
Index	p. 557
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