Digital Design With Cpld Applications and Vhdl

by Dueck, Robert K.

• ISBN13: 9780766811607
• ISBN10: 0766811603
• Edition: CD
• Format: Paperback
• Copyright: 2000-06-28
• Publisher: CENGAGE Delmar Learning

Summary

This Second Edition continues to use programmable logic as the primary vehicle for teaching digital design principles, and maintains its cutting-edge status by updating to Altera's newest Quartus II software, the most current method of digital design implementation. This Windows-based software allows users to design, test, and program CPLD designs in text-based (VHDL) and graphic (schematic entry) formats. The Second Edition introduces CPLDs earlier in the teaching sequence, laying a solid foundation for more advanced principles without neglecting underlying digital fundamentals such as Boolean algebra, logic minimization, and combinational and sequential circuits. VHDL and Quartus II applications are provided throughout.

Author Biography

Robert Dueck now teaches digital design at Red River College.

Table of Contents

Preface	ix
Basic Principles of Digital Systems	1	(24)
Digitial Versus Analog Electronics	2	(1)
Digitial Logic Levels	3	(1)
The Binary Number System	4	(8)
Hexadecimal Numbers	12	(3)
Digitial Waveforms	15	(10)
Logic Functions and Gates	25	(32)
Basic Logic Functions	26	(5)
Logic Switches and LED Indicators	31	(3)
Derived Logic Functions	34	(3)
DeMorgan's Theorems and Gate Equivalence	37	(4)
Enable and Inhibit Properties of Logic Gates	41	(5)
Integrated Circuit Logic Gates	46	(11)
Boolean Algebra and Combinational Logic	57	(58)
Boolean Expressions, Logic Diagrams and Truth Table	58	(9)
Sum-of-Products (SOP) and Product-of-Sums (POS) Forms	67	(6)
Theorems of Boolean Algebra	73	(13)
Simplifying SOP and POS Expressions	86	(4)
Simplification by the Karnaugh Map Method	90	(25)
Introduction to PLDs and MAX+PLUS II	115	(40)
What is a PLD?	116	(2)
Programming PLDs using MAX+PLUS II	118	(2)
Graphic Design File	120	(7)
Compling MAX+PLUS II Files	127	(2)
Hierarchical Design	129	(4)
Text Design File (VHDL)	133	(7)
Creating a Physical Design	140	(15)
Combinational Logic Functions	155	(66)
Decoders	156	(23)
Encoders	179	(6)
Multiplers	185	(12)
Demultiplexers	197	(6)
Magnitude Comparators	203	(5)
Parity Generators and Checkers	208	(13)
Digital Arithmetic and Arithmetic Circuits	221	(54)
Digital Arithmetic	222	(3)
Representing Signed Binary Numbers	225	(2)
Signed Binary Arithmetic	227	(5)
Hexadecimal Arithmetic	232	(3)
Numeric and Alphanumeric Codes	235	(4)
Binary Adders and Subtractors	239	(20)
BCD Adders	259	(4)
Carry Generation in MAX+PLUS II	263	(12)
Introduction to Sequential Logic	275	(54)
Latches	276	(3)
NAND/NOR Latches	279	(10)
Gated Latches	289	(9)
Edge-Triggered D Flip-Flops	298	(5)
Edge-Triggered JK Flip-Flops	303	(7)
Edge-Triggered T Flip-Flops	310	(2)
Timing Parameters	312	(17)
Introduction to Programmable Logic Architectures	329	(34)
Programmable Sum-of-Products Arrays	330	(2)
PAL Fuse Matrix and Combinational Outputs	332	(4)
PAL Outputs with Programmable Polarity	336	(5)
PAL Devices with Registered Outputs	341	(4)
Universal PAL and Generic Array Logic	345	(6)
Max7000s CPLD	351	(3)
FLEX10K CPLD	354	(9)
Counters and Shift Registers	363	(94)
Basic Concepts of Digital Counters	364	(5)
Synchronous Counters	369	(7)
Design of Synchronous Counters	376	(9)
Programming Binary Counters in VHDL	385	(3)
Control Options for Synchronous Counters	388	(15)
Programming Presettable and Bidirectional Counters in VHDL	403	(10)
Shift Registers	413	(13)
Programming Shift Registers in VHDL	426	(12)
Shift Register Counters	438	(19)
State Machine Design	457	(40)
State Machines	457	(2)
State Machines with No Control Inputs	459	(7)
State Machines with Control Inputs	466	(9)
Switch Debouncer for a Normally Open Pushbutton Switch	475	(9)
Unused States in State Machines	484	(6)
Traffic Light Controller	490	(7)
Logic Gate Circuitry	497	(68)
Electrical Characteristics of Logic Gates	498	(4)
Propagation Delay	502	(3)
Fanout	505	(5)
Power Dissipation	510	(4)
Noise Margin	514	(2)
Interfacing TTL and CMOS Gates	516	(2)
Internal Circuitry of TTL gates	518	(22)
Internal Circuitry of CMOS Gates	540	(11)
TTL and CMOS Variations	551	(14)
Interfacing Analog and Digital Circuitry	565	(56)
Analog and Digital Signals	566	(5)
Digital-to-Analog Conversion	571	(20)
Analog-to-Digital Conversion	591	(14)
Data Acquisition	605	(16)
Memory Devices and Systems	621	(36)
Basic Memory Concepts	622	(8)
Random Access Read/Write Memory (RAM)	630	(6)
Read Only Memory (ROM)	636	(9)
Sequential Memory: FIFO and LIFO	645	(1)
Dynamic RAM Modules	646	(2)
Memory Systems	648	(9)
Appendix A Altera UP-1 User's Guide	657	(32)
Appendix B VHDL Language Reference	689	(13)
Appendix C Data Sheets	702	(64)
Appendix D CMOS Handling Precautions	766	(2)
Appendix E EPROM/ROM Data for a Digital Function Generator	768	(7)
Answers to Selected Odd-Numbered Problems	775	(64)
Index	839