Summary

Digital Design of Signal Processing Systems discusses a spectrum of architectures and methods for effective implementation of algorithms in hardware (HW). Encompassing all facets of the subject this book includes conversion of algorithms from floating-point to fixed-point format, parallel architectures for basic computational blocks, Verilog Hardware Description Language (HDL), SystemVerilog and coding guidelines for synthesis.The book also covers system level design of Multi Processor System on Chip (MPSoC); a consideration of different design methodologies including Network on Chip (NoC) and Kahn Process Network (KPN) based connectivity among processing elements. A special emphasis is placed on implementing streaming applications like a digital communication system in HW. Several novel architectures for implementing commonly used algorithms in signal processing are also revealed. With a comprehensive coverage of topics the book provides an appropriate mix of examples to illustrate the design methodology.Key Features: A practical guide to designing efficient digital systems, covering the complete spectrum of digital design from a digital signal processing perspective Provides a full account of HW building blocks and their architectures, while also elaborating effective use of embedded computational resources such as multipliers, adders and memories in FPGAs Covers a system level architecture using NoC and KPN for streaming applications, giving examples of structuring MATLABreg; code and its easy mapping in HW for these applications Explains state machine based and Micro-Program architectures with comprehensive case studies for mapping complex applications

Author Biography

Dr. Shoab Ahmed Khan, Center for Advanced Studies in Engineering (CASE), Islamabad, Pakistan
Dr. Shoab Ahmed Khan is currently Associate Professor of Computer Engineering at the National University of Sciences and Technology, as well as CEO for the Center for Advanced Research (CARE), both in Pakistan. He is also Associate Adjunct Professor of Electrical Engineering at Michigan State University in the USA. Additionally, Dr. Khan has had over 14 years industrial experience in companies such as Scientific Atlanta, Picture Tel, Cisco Systems and Avaz Networks. He is one of five recipients of the National Education Award 2001 in the category of 'Outstanding Services to Science and Technology', and NCR National Excellence Award 2007 in the category of IT education. He was also awarded a Presidential Gold Medal for being the best teacher of NUST 2006.

Preface
Acknowledgement
Introduction to Digital Design of Signal Processing Systems
Fueling the Innovation: Moore's Law
Digital Systems
Examples of Digital Systems
Example: The Backplane of a Router
Digital Design Process
Digital Design Competing Objectives
Synchronous Digital Hardware Systems
Design Strategies
References
Digital Design Using HDL
Introduction to Verilog
System Design Flow
Verilog HDL
Four Levels of Abstraction
Verification in HW Design
System Verilog
Exercise
References
System Design Flow and Fixed-Point Arithmetic
System Design Flow
Representations and Numbers
Floating-point Format
Qn.m Format for Fixed-point Arithmetic
Floating-Point to Fixed-Point Conversion
Block Floating-Point Format
Digital Filters Forms
Exercise
References
DSP System Representations and Mapping on Fully Dedicated Architecture
Introduction
Discrete Real-Time System
Synchronous Digital Hardware Systems
Kahn Process Network (KPN)
Representation Methods of DSP systems
Performance Measures
Fully Dedicated Architecture
Pipelining in Fully Dedicated Architecture
Selecting Basic Building Blocks
DFG to HW Synthesis
Exercise
References
Design Options for Basic Building Blocks
Introduction
Embedded Processors and Arithmetic Units in FPGAs
Instantiation of Embedded Blocks
Basic Building Blocks
Adders
Barrel Shifter
Parallel Multiplier Architectures
Cary Save Adder (CSA) and Compressors
Compression Trees
2's Complement Signed Multiplier
Compression Trees for Multi Operand Addition
Algorithm Transformations for CSA
Exercise
References
Multiplierless Multiplication by Constants
Introduction
Canonic Sign Digit (CSD) Representation
Minimum Signed Digit Representation
Multiplication by Constant in Signal Processing Algorithm
Fully Dedicated Architecture for Direct Form FIR Filter
Transposed Direct Form FIR Filter
Complexity Reduction
Distributed Arithmetic
FFT Architecture using FIR Filter Structure
Exercise
References
Pipelining, Retiming, Look-ahead Transformation and Polyphase Decomposition
Introduction
Pipelining and Retiming
Digital Design of Feedback Systems
C-slow Retiming
Look Ahead Transformation for IIR filters
Polyphase Structure for Decimation and Interpolation Applications
Exercise
References
Unfolding and Folding Architectures
Introduction
Sampling Rate Considerations
Unfolding Techniques
Folding Techniques
Folding Regular Structured DFGs
Mathematical Transformation for Folding
Exercise
References
Finite State Machine-based Design
Time Shared Architecture Design Examples
Sequencing and Control
Algorithm State Machine Representation
FSM Optimization for Low Power and Area
Design for Testability
Testing FSMs
Sequence Conformance
Coverage Metrics for Design Validation
Methods for Reducing Power of a State Machine
Exercise
References
Micro program State Machines
Introduction
Micro programmed Controller
Counter-based State Machine Implementation
A Loadable Counter-based Micro-Program FSM
Counter-based Micro-Program FSM with Conditional Branching
Register Based Controller
Micro-program State Machine with Subroutine Support
Micro-program State Machine with Nested Loop Support
Design Example of a Wavelet Processor
References
Micro-Programmed-based Adaptive Filtering Applications
Introduction
Adaptive Filters Configurations
Adaptive Algorithms
Channel Equalizer using NLMS
Echo Canceller
Micro-Coded State Machine based Design for Adaptive Algorithm
Architecture of LEC Micro-coded Accelerator
Exercise
References
Exploring Design Options for CORDIC based DDFS Architectures
Introduction
Direct Digital Frequency Synthesizer
Design of a Basic DDFS
CORDIC Algorithm
HW Mapping of Modified CORDIC Algorithm
Exercise
References
Digital Design of Communication Systems
Top-level Design Options
Digital Communication System
Source Encoding
Encryption
Channel Coding
Digital Baseband Modulation
Exercise
References
Table of Contents provided by Publisher. All Rights Reserved.

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