Digital Integrated Circuit Design

by Martin, Ken

• ISBN13: 9780195125849
• ISBN10: 0195125843
• Format: Hardcover
• Copyright: 1999-09-30
• Publisher: Oxford University Press

Summary

Working from the fundamentals of transistor-level design and building up to system-level considerations, Digital Integrated Circuit Design shows students with minimal background in electronics how to design state-of-the-art high performance digital integrated circuits. Ideal as an upper-level undergraduate text, it can also be used in first-year graduate courses and as a reference for practicing engineers. Digital Integrated Circuit Design: · Presents transistor-level details first, building up to system considerations · Emphasizes CMOS technology but also includes in-depth explanations of designing in bipolar, BiCMOS, and GaAs technologies · Features modern, well-designed examples and problems · Covers important system-level considerations such as timing, pipelining, clock distribution, and system building blocks in detail · Discusses key elements of semiconductor physics, integrated circuit processing, transistor-level design, logic-level design, system-level design, testing, and more · Provides physical and intuitive explanations throughout · Emphasizes conceptual thinking and design methodology over detailed circuit analysis techniques

Table of Contents

Preface	xiv
The Basics	1	(34)
Simple NMOS Logic Gates	2	(6)
Simple CMOS Logic Gates	8	(6)
Computer Simulation	14	(5)
Transfer Curves and Noise Margins	19	(4)
Gate Delays and Rise and Fall Times	23	(2)
Transient Response	25	(4)
An RC Approximation to the Transient Response of a CMOS Inverter	29	(2)
Summary	31	(1)
Bibliography	32	(1)
Problems	32	(3)
Processing, Layout, and Related Issues	35	(30)
CMOS Processing	35	(13)
The Silicon Wafer	36	(1)
Photolithography and Well Definition	36	(2)
Diffusion and Ion Implantation	38	(2)
Chemical Vapor Deposition and Defining the Active Regions	40	(1)
Field Implants and the Field Oxide	40	(1)
Growing the Field Oxide	41	(1)
The Gate Oxide and Threshold Voltage Adjusts	42	(1)
Polysilicon Gate Formation	43	(1)
Implanting the Junctions, Depositing SiO2, and Opening Contact Holes	44	(2)
Annealing, Depositing and Patterning Metal, and Overglass Deposition	46	(1)
Processing Alternatives	46	(2)
Bipolar Processing	48	(1)
CMOS Layout and Design Rules	48	(11)
Advanced CMOS Processing	59	(2)
Lightly Doped Drains	59	(2)
Bibliography	61	(1)
Problems	61	(4)
Integrated-Circuit Devices and Modeling	65	(104)
Simplified Transistor Modeling	66	(5)
MOS Transistors	66	(3)
Bipolar Transistors	69	(2)
Semiconductors and pn Junctions	71	(15)
Diodes	72	(2)
Reverse-Biased Diodes	74	(4)
Graded Junctions	78	(2)
Large-Signal Junction Capacitance	80	(3)
Forward-Biased Junctions	83	(1)
Junction Capacitance of a Forward-Biased Diode	84	(1)
Schottky Diodes	85	(1)
MOS Transistors	86	(15)
Symbols for MOS Transistors	88	(1)
Basic Operation	89	(6)
Large-Signal Modeling	95	(3)
Body Effect	98	(1)
p-Channel Transistors and Depletion Transistors	99	(1)
Small-Signal Modeling	100	(1)
Advanced MOS Modeling	101	(8)
Scaling	102	(2)
Short-Channel Effects	104	(1)
Subthreshold Operation	105	(1)
Leakage Currents	106	(1)
Latch-Up	106	(3)
Bipolar-Junction Transistors	109	(9)
Basic Operation	110	(3)
Large-Signal Modeling	113	(1)
Base Charge Storage in the Active Region	114	(1)
Base Charge Storage of a Saturated Transistor	114	(2)
Small-Signal Modeling	116	(2)
SPICE-Modeling Parameters	118	(4)
Diode Model Parameters	118	(1)
MOS Transistors Parameters	119	(1)
Bipolar-Junction Transistor Parameters	120	(2)
Appendix	122	(33)
Diode Exponential Relationship	122	(3)
Diode Diffusion Capacitance	125	(1)
Small-Signal Model of a Forward-Biased Diode	126	(2)
MOS Threshold Voltage and the Body Effect	128	(2)
MOS Triode Relationship	130	(3)
Small-Signal MOS Modeling in the Active Region	133	(8)
Small-Signal MOS Modeling in the Triode and Cutoff Regions	141	(4)
Bipolar Transistor Exponential Relationship	145	(3)
Base Charge Storage of an Active Bipolar-Junction Transistor	148	(1)
Small-Signal Bipolar Modeling	148	(7)
SPICE Simulations	155	(3)
Simulation of Example 3.6	155	(1)
Simulation of Example 3.7	156	(2)
Bibliography	158	(1)
Problems	158	(5)
Device Model Summary	163	(6)
Traditional MOS Design	169	(68)
Pseudo-NMOS Logic	169	(14)
Using a p-Channel Transistor to Realize a Current Source	170	(1)
A Pseudo-NMOS Inverter	171	(1)
Inverter Threshold Voltage (Vth)	172	(1)
Typical Output High Voltage VoH	173	(1)
Typical Output Low Voltage VoL	174	(1)
Gain at the Gate Threshold Voltage	175	(4)
Transient Response	179	(1)
Rise Time	179	(1)
Fall Time	180	(3)
Pseudo-NMOS Logic Gates	183	(1)
Transistor Equivalency	184	(16)
Resistor Equivalency	188	(2)
Evaluating the Logic Function of an NMOS Gate	190	(1)
Realizing Complex Pseudo-NMOS Gate	191	(3)
Choosing Transistor Sizes	194	(2)
Power Dissipation	196	(1)
Other Pseudo-NMOS Circuits	197	(1)
NMOS Logic with Depletion-Load Transistors	198	(2)
CMOS Logic	200	(12)
CMOS Inverter	200	(1)
Threshold Voltage	201	(1)
Inverter Gain at Vin = Vth	202	(2)
Transient Response	204	(1)
The Effect of Transistor Sizes on the Transient Responses	205	(4)
Power Dissipation	209	(3)
CMOS Gate Design	212	(8)
Traditional Logic Design	212	(8)
SPICE Simulations	220	(9)
Simulation of Examples 4.1, 4.3, 4.5, and 4.6	220	(2)
Simulation of Example 4.4	222	(1)
Simulation of the Circuit of Fig. 4.22	223	(1)
Simulation of the Circuit of Fig. 4.24	224	(1)
Simulation of Examples 4.13 and 4.15	225	(2)
Simulation of Example 4.14	227	(1)
Simulation of the Circuit of Fig. 4.26	228	(1)
Bibliography	229	(1)
Problems	229	(8)
Transmission-Gate and Fully Differential CMOS Logic	237	(23)
Transmission-Gate Logic Design	237	(15)
Voltage Drop of n-Channel X Gates	242	(3)
n-Channel Pass Transistors versus CMOS Transmission Gates	245	(1)
Full-Swing n-Channel X-Gate Logic	246	(1)
Leakage Currents	247	(1)
Clock Feedthrough	248	(4)
Differential CMOS Circuits	252	(4)
Bibliography	256	(1)
Problems	256	(4)
CMOS Timing and I/O Considerations	260	(24)
Delay of MOS Circuits	260	(14)
Gate Capacitances	260	(1)
Junction Capacitances	261	(4)
Interconnect Capacitances	265	(2)
Delay of RC Ladder Structure	267	(3)
Delay of CMOS Logic Gates	270	(2)
Using SPICE for Req and Cj Calculations	272	(2)
Input/Output Circuits	274	(6)
Input-Protection Circuits	274	(1)
Output Circuits and Driving Large Capacitors	275	(1)
Three-State Outputs	276	(2)
Bonding Pads and Wires	278	(2)
Bibliography	280	(1)
Problems	280	(4)
Latches, Flip-Flops, and Synchronous System Design	284	(40)
CMOS Clocked Latches	285	(9)
Static CMOS Digital Latches	285	(6)
Static Random-Access Memory Cell	291	(2)
Dynamic CMOS Latches	293	(1)
Flip-flops	294	(7)
D Flip-flop	295	(1)
SR Flip-flop	296	(1)
Edge-Triggered SR Flip-flop	297	(1)
JK Flip-flop	298	(3)
T Flip-flop	301	(1)
CMOS Flip-flops	301	(3)
Synchronous System Design Techniques	304	(8)
Pipelined Systems	305	(1)
System Clock Issues	306	(3)
Master Clock Distribution	309	(3)
Synchronous System Examples	312	(9)
Gray-Code Counter	313	(4)
Register-Based Controllers	317	(4)
Bibliography	321	(1)
Problems	321	(3)
Bipolar and BiCMOS Logic Gates	324	(40)
Emitter-Coupled Logic Gates	325	(9)
Emitter-Coupled Differential Pairs	325	(2)
Emitter-Coupled Logic	327	(5)
Terminating Emitter-Coupled Logic	332	(1)
Temperature Sensitivity	333	(1)
Current-Mode Logic	334	(16)
Current-Mode Logic Gates	335	(9)
Current-Mode Logic Latches	344	(2)
Current-Mode Logic Flip-flops	346	(1)
Differential Current-Mode Logic to Single-Ended Current-Mode Logic	346	(3)
Current-Mode Logic Buffers	349	(1)
BiCMOS	350	(8)
BiCMOS Logic Gates	351	(4)
Alternative BiCMOS Approaches and Circuits	355	(3)
SPICE Simulatins	358	(2)
Bibliography	360	(1)
Problems	360	(4)
Advanced CMOS Logic Design	364	(34)
Pseudo-NMOS and Dynamic Precharging	364	(6)
Domino-CMOS Logic	370	(7)
Domino Logic without Inverters	373	(1)
Static Domino Logic	374	(1)
Charge Sharing of Domino Logic Gates	374	(2)
Multiple-Output Domino Logic Circuits	376	(1)
No-Race-Logic	377	(3)
Single-Phase Dynamic Logic	380	(2)
Differential CMOS	382	(6)
Differential Split-Level CMOS Logic	385	(2)
Differential Pass-Transistor Logic	387	(1)
Dynamic Differential Logic	388	(5)
Differential Domino Logic	388	(2)
Differential NORA Logic	390	(1)
Regenerative Differential Logic	390	(3)
Bibliography	393	(1)
Problems	394	(4)
Digital Integrated System Building Blocks	398	(39)
Multiplexors and Decoders	398	(5)
Barrel Shifters	403	(2)
Counters	405	(3)
Digital Adders	408	(11)
Single-Bit Adders	408	(4)
Ripple-Carry Adders	412	(1)
Carry-Save Adders	412	(2)
Carry-Lookahead, Carry-Propagate, and Carry-Select Adders	414	(4)
Digital Subtractors	418	(1)
Digital Multipliers	419	(8)
Modified Booth Multipliers	422	(5)
Programmable Logic Arrays	427	(6)
Pseudo-NMOS PLAs	427	(2)
Self-Timed Dynamic PLAs	429	(2)
Two-Phase PLA	431	(2)
Bibliography	433	(1)
Problems	433	(4)
Integrated Memories	437	(46)
Static Random-Access Memories	438	(2)
Static Random-Access Memory Storage Cells	440	(12)
Sense Amplifier	449	(3)
Address Buffers and Decoders	452	(3)
Dynamic Bus Precharge and Address-Transition-Detect Circuits	455	(2)
Modifications for Large Static Random-Access Memories	457	(1)
Dynamic Random-Access Memories	458	(6)
Dynamic Memory Cells	459	(2)
Dynamic Random-Access Memory Sense Amplifiers	461	(2)
Level-Boosted Word Lines	463	(1)
Read-Only Memories	464	(14)
Mask-Programmable Read-Only Memories	465	(2)
Sensing Read-Only Memory Cells	467	(3)
Programmable Read-Only Memories	470	(5)
NAND Architectures	475	(2)
Charge Pumps	477	(1)
Bibliography	478	(1)
Problems	479	(4)
Gaas Digital Circuits	483	(26)
Introduction	483	(1)
GaAs Processing and Components	484	(3)
MESFET Modeling	487	(2)
MESFET Second-Order Effects	489	(1)
Back-gating	489	(1)
MESFET Hysteresis	489	(1)
Logic Design with MESFETs	490	(3)
Buffered-FET Logic	491	(2)
Capacitively Enhanced Logic	493	(10)
Direct-Coupled Logic	495	(3)
Source-Coupled Logic	498	(2)
Dynamic GaAs Logic	500	(3)
GaAs Logic Family Comparison	503	(1)
Heterojunction Bipolar Technology	503	(3)
Bibliography	506	(1)
Problems	506	(3)
Digital System Testing	509	(26)
Conservative Design Principles	510	(1)
Scan-Design Techniques	511	(7)
Level-Sensitive Scan Design	512	(2)
Level-Sensitive Scan Design Implementation Issues	514	(3)
Related Test-Design Techniques	517	(1)
Localized Test-Vector Generation and Test-Output Compression Techniques	518	(8)
Maximal-Length Linear-Feedback Shift Registers	518	(3)
Signature Analysis	521	(1)
Built-in Logic-Block Observation	522	(4)
Boundary-Scan Testing	526	(6)
Boundary-Scan Architecture	527	(3)
Boundary-Scan Testing Methodology	530	(2)
Bibliography	532	(1)
Problems	533	(2)
Index	535