Digital Logic Design Principles

by Balabanian, Norman; Carlson, Bradley

• ISBN13: 9780471293514
• ISBN10: 0471293512
• Edition: 1st
• Format: Hardcover
• Copyright: 2000-11-17
• Publisher: Wiley

Summary

This book is an introduction on the principles of digital logic circuits. While providing coverage to the usual topics in combinational and sequential circuit principles, it also includes a chapter on the use of the hardware description language ABEL in the design of circuits using PLDs and a chapter on computer organization.

Author Biography

Norman Balabanian and Bradley Carlson are the authors of Digital Logic Design Principles, published by Wiley.

Table of Contents

Number Representation, Codes, and Code Conversion	1	(34)
Systems: Digital and Analog	1	(2)
Hardware, Software, and Firmware	3	(1)
Number Systems	4	(13)
Binary and Other Number Systems	5	(2)
Base Conversions	7	(1)
Converting to the Decimal Systems	7	(1)
Converting from The Decimal System	7	(2)
From Octal or Hexadecimal to Binary	9	(1)
Binary Arithmetic	10	(1)
Addition	10	(1)
Subtraction	11	(1)
Multiplication	11	(1)
Division	11	(1)
Complements: Two's and One's	12	(2)
Addition of Binary Numbers	14	(3)
Codes and Code Conversion	17	(5)
Binary-Coded Decimal	18	(1)
Weighted Codes	18	(1)
Gray Code	19	(1)
Seven-Segment Code	20	(1)
Alphanumeric Codes	21	(1)
Error Detection and Correction	22	(12)
Error-Detecting Codes	22	(2)
Error-Correcting Codes	24	(1)
Hamming Codes	25	(2)
Summary and Review	27	(1)
Problems	28	(6)
Switching Algebra And Logic Gates	34	(47)
Boolean Algebra	34	(7)
Duality Principle	36	(1)
Fundamental Theorems	36	(3)
Switching Algebra	39	(2)
Switching Operations	41	(2)
The AND Operation	41	(1)
The OR Operation	41	(1)
The NOT Operation	42	(1)
Commentary	42	(1)
Switching Expressions	43	(5)
Minterms, Maxterms, and Canonic Forms	44	(2)
Generalization of De Morgan's Law	46	(2)
Switching Functions	48	(5)
Switching Operations on Switching Functions	49	(1)
Number of Terms in Canonic Forms	50	(1)
Shannon's Expansion Theorem	51	(1)
Sum-of-Products Form	51	(1)
Product-of-Sums Form	52	(1)
Other Switching Operations	53	(1)
Exclusive	53	(1)
NAND, NOR, and XNOR Operations	54	(1)
Universal Sets of Operations	54	(2)
Logic Gates	56	(3)
Alternative Forms of NAND and NOR Gates	57	(1)
Exclusive-OR Gates	58	(1)
Commentary	58	(1)
Positive, Negative, and Mixed Logic	59	(2)
Some Practical Matters Regarding Gates	61	(9)
Logic Families	62	(1)
Input/Output Characteristics of Logic Gates	63	(4)
Fan-out and Fan-in	67	(1)
Buffers	67	(1)
Power Consumption	68	(1)
Noise Margin	68	(1)
Speed and Propagation Delay	69	(1)
Integrated Circuits	70	(4)
Some Characteristics of ICs	71	(2)
Design Economy	73	(1)
Application-Specific ICs	74	(1)
Wired Logic	74	(7)
Tristate (High-Impedance) Logic Gates	74	(1)
Open-Collector and Open-Drain Logic Gates	75	(1)
Chapter Summary and Review	76	(1)
Problems	77	(4)
Representation and Implementation of Logic Functions	81	(51)
Minterm and Maxterm Lists	81	(3)
Minterm Lists and Sum-of-Products Form	82	(1)
Maxterm Lists and Product-of-Sums Form	83	(1)
Logic Maps	84	(8)
Logical Adjacency and Geometrical Adjacency	84	(5)
Cubes of Order k	89	(3)
Minimal Realizations of Switching Functions	92	(9)
Irreducible and Minimal Expressions	92	(1)
Prime Implicants	93	(2)
Minimal Sum-of-Products Expressions	95	(2)
Minimal Product-of-Sums Expressions	97	(1)
Two-Level Implementations	98	(1)
AND-OR Implementation	98	(1)
NAND Implementation	99	(1)
OR-AND Implementation	100	(1)
Implementation of Logic Expressions	101	(4)
Analysis	103	(1)
Features of Gate Circuits	104	(1)
Timing Diagrams	105	(2)
Incompletely Specified Functions	107	(2)
Don't-Cares	107	(2)
Comparators	109	(3)
2-Bit Comparators	109	(2)
Generalization	111	(1)
4-Bit Comparators	111	(1)
Comparators of Even Numbers of Bits	112	(1)
Comparators of Odd Numbers of Bits	112	(1)
Prime Implicant Determination: Tabular Method	112	(7)
Representations of Adjacent k-cubes	113	(1)
Ranking by Index	114	(2)
Incompletely Specified Functions	116	(1)
Selection of a Minimal Expression	117	(1)
Completely Specified Functions	117	(2)
Handling Don't-Cares	119	(1)
Multiple-Output Circuits	119	(13)
Chapter Summary and Review	120	(1)
Problems	121	(11)
Combinational Logic Design	132	(36)
Binary Adders	132	(10)
Full Adder	133	(2)
Ripple-Carry Adder	135	(1)
Carry-Lookahead Adder	136	(4)
Binary Subtractor	140	(1)
Two's-Complement Adder and Subtractor	140	(1)
One's-Complement Adder and Subtractor	141	(1)
Multiplexers	142	(5)
Multiplexers as General-Purpose Logic Circuits	145	(2)
Decoders and Encoders	147	(5)
Demultiplexers	147	(2)
n-to-2n-Line Decoder	149	(1)
Tree Decoder	150	(1)
Decoders as General-Purpose Logic Circuits: Code Conversion	150	(2)
Read-Only Memory (ROM)	152	(3)
Other LSI Programmable Logic Devices	155	(13)
Programmed Logic Array (PLA)	155	(2)
Programmed Array Logic (PAL)	157	(2)
Chapter Summary and Review	159	(1)
Problems	160	(8)
Sequential Circuit Components	168	(30)
Definitions and Basic Concepts	168	(4)
Latches and Flip-Flops	172	(14)
SR Latch	172	(4)
Timing Problems and Clocked SR Latches	176	(1)
JK Latch	177	(1)
Master-Slave Latch	178	(1)
A Possible Design	179	(1)
An Alternative Master-Slave Design	180	(1)
Edge-Triggering Parameters	181	(1)
Delay (D) Flip-flops	182	(1)
Edge-Triggered D Flip-Flop	182	(2)
T Flip-Flop	184	(1)
Flip-flop Excitation Requirements	185	(1)
Registers	186	(12)
Serial-Load Shift Register	187	(1)
Parallel-Load Shift Register	188	(1)
Parallel-to-Serial Conversion	189	(1)
Universal Registers	190	(2)
Chapter Summary and Review	192	(1)
Problems	192	(6)
Synchronous Sequential Machines	198	(56)
Basic Concepts	198	(8)
State Diagram	200	(3)
State Table	203	(1)
Constructing a State Table from a State Diagram	203	(3)
State Assignments	206	(7)
Analysis	208	(1)
Rules of Thumb for Assigning States	209	(4)
General Design Procedure	213	(6)
Mealy Machine	213	(5)
Moore Machine	218	(1)
State Equivalence and Machine Minimization	219	(4)
Distinguishability and Equivalence	220	(1)
Machine Minimization	221	(2)
Machines with Finite Memory Spans	223	(4)
Machines with Finite Input Memory	224	(1)
Machines with Finite Output Memory	225	(2)
Finite-Memory Machines	227	(1)
Synchronous Counters	227	(6)
Single-Mode Counters	228	(1)
Unit-Distance Counters	228	(2)
Ring Counters	230	(1)
Hang-up States	231	(1)
Multimode Counters	232	(1)
Modulo-6 Up-Down Counter	232	(1)
Algorithmic State Machines	233	(5)
Basic Principles	234	(4)
Asynchronous Inputs	238	(16)
Asynchronous communication (Handshaking)	239	(2)
Chapter Summary and Review	241	(1)
Problems	242	(12)
Asynchronous Sequential Machines	254	(36)
The Fundamental-Mode Model	255	(1)
The Flow Table	256	(5)
Primitive Flow Tables	256	(4)
Assigning Outputs to Unstable States	260	(1)
Reduction of Incompletely Specified Machines	261	(9)
The Merger Table	262	(1)
Compatibility	262	(1)
Construction of the Merger Table	263	(2)
Determination of Minimal, Closed Covers	265	(2)
Transition Tables	267	(3)
Races and Cycles	270	(5)
Critical and Noncritical Races	271	(2)
Cycles and Oscillations	273	(2)
Hazards	275	(15)
Static Hazards	275	(5)
Dynamic Hazards	280	(1)
Essential Hazards	280	(2)
Chapter Summary and Review	282	(1)
Problems	282	(8)
Design Using Hardware Description Languages	290	(35)
The Hardware Description Language ABEL	291	(15)
Adder Specification in ABEL	292	(2)
Behavioral versus Operational Description	294	(2)
Adder Specification in ABEL	296	(1)
Sequential Circuit Specification in ABEL	297	(3)
Don't-Care Conditions in ABEL	300	(1)
Hierarchical Specifications in ABEL	301	(5)
Programmable Logic Devices (PLDs)	306	(11)
Complex Programmable Logic Devices	310	(5)
Field-Programmable Gate Arrays	315	(2)
The Design Flow for HDL Specifications	317	(8)
Synthesis and Technology Mapping of ABEL Specifications	318	(3)
Simulation of ABEL Specifications	321	(1)
Chapter Summary and Review	322	(1)
Problems	323	(2)
Computer Organization	325	(32)
Control and Datapath Units of a Processor	325	(9)
Datapath Unit	326	(1)
Control Unit	327	(1)
Serial Multiplier Example	327	(7)
Basic Stored-Program Computer	334	(6)
Central Processing Unit (CPU)	335	(1)
Simple Datapath	335	(3)
Controlling the Simple Datapath	338	(2)
Control-Unit Implementations	340	(7)
Hard-Wired Control Unit	340	(2)
Memory and I/O Interface	342	(1)
Micro-Programmed Control Unit	343	(4)
Contemporary Microprocessor Architectures	347	(6)
Instruction Pipelining	347	(2)
Parallel Hardware Units	349	(1)
Memory Hierarchy	350	(1)
Complex Instruction Set Computer (CISC)	350	(2)
Reduced Instruction Set Computer (RISC)	352	(1)
Microcontroller Architectures	353	(4)
Chapter Summary and Review	354	(1)
Problems	355	(2)
Appendix MOSFETS and Bipolar Junction Transistors	357	(5)
Bibliography	362	(3)
Index	365