Digital Signal Processing With Field Programmable Gate Arrays (Book with CD-ROM)

by Meyer-Baese, Uwe

• ISBN13: 9783540211198
• ISBN10: 3540211195
• Edition: 2nd
• Format: Hardcover
• Copyright: 2004-06-01
• Publisher: SPRINGER

Summary

Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing as novel FPGA families are replacing ASICs and PDSPs for front-end digital signal processing algorithms. So the efficient implementation of these algorithms is critical and is the main goal of this book. It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems. A case study in the first chapter is the basis for more than 30 design examples throughout. The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, and advanced algorithms with high future potential. Each chapter contains exercises. The VERILOG source code and a glossary are given in the appendices, while the accompanying CD-ROM contains the examples in VHDL and Verilog code as well as the newest Altera "Baseline" software. This edition has a new chapter on adaptive filters, new sections on division and floating point arithmetics, an up-date to the current Altera software, and some new exercises.

Table of Contents

Preface	vii
Preface to Second Edition	xi
Introduction	1	(30)
Overview of Digital Signal Processing (DSP)	1	(2)
FPGA Technology	3	(7)
Classification by Granularity	3	(2)
Classification by Technology	5	(1)
Benchmark for FPLs	6	(4)
DSP Technology Requirements	10	(2)
FPGA and Programmable Signal Processors	11	(1)
Design Implementation	12	(19)
FPGA Structure	16	(3)
The Altera EPF10K70RC240-4	19	(3)
Case Study: Frequency Synthesizer	22	(5)
Exercises	27	(4)
Computer Arithmetic	31	(78)
Introduction	31	(1)
Number Representation	32	(18)
Fixed-Point Numbers	32	(3)
Unconventional Fixed-Point Numbers	35	(12)
Floating-Point Numbers	47	(3)
Binary Adders	50	(8)
Pipelined Adders	52	(5)
Modulo Adders	57	(1)
Binary Multipliers	58	(5)
Multiplier Blocks	62	(1)
Binary Dividers	63	(13)
Linear Convergence Division Algorithms	66	(5)
Fast Divider Design	71	(5)
Array Divider	76	(1)
Floating-point Arithmetic Implementation	76	(11)
Fixed-point to Floating-point Format Conversion	77	(2)
Floating-point to Fixed-point Format Conversion	79	(1)
Floating-point Multiplication	80	(1)
Floating-point Addition	81	(2)
Floating-point Division	83	(2)
Floating-point Reciprocal	85	(1)
Floating-point Synthesis Results	86	(1)
Multiply-Accumulator (MAC) and Sum of Product (SOP)	87	(7)
Distributed Arithmetic Fundamentals	88	(3)
Signed DA Systems	91	(1)
Modified DA Solutions	92	(2)
Computation of Special Functions Using Cordic	94	(15)
Cordic Architectures	98	(5)
Exercises	103	(6)
Finite Impulse Response (FIR) Digital Filters	109	(38)
Digital Filters	109	(1)
FIR Theory	110	(6)
FIR Filter with Transposed Structure	111	(3)
Symmetry in FIR Filters	114	(1)
Linear-phase FIR Filters	115	(1)
Designing FIR Filters	116	(5)
Direct Window Design Method	117	(2)
Equiripple Design Method	119	(2)
Constant Coefficient FIR Design	121	(26)
Direct FIR Design	122	(4)
FIR Filter with Transposed Structure	126	(2)
FIR Filter Using Distributed Arithmetic	128	(15)
Exercises	143	(4)
Infinite Impulse Response (IIR) Digital Filters	147	(28)
IIR Theory	150	(3)
IIR Coefficient Computation	153	(3)
Summary of Important IIR Design Attributes	155	(1)
IIR Filter Implementation	156	(6)
Finite Wordlength Effects	160	(1)
Optimization of the Filter Gain Factor	161	(1)
Fast IIR Filter	162	(13)
Time-domain Interleaving	163	(2)
Clustered and Scattered Look-Ahead Pipelining	165	(3)
IIR Decimator Design	168	(1)
Parallel Processing	168	(3)
IIR Design Using RNS	171	(1)
Exercises	172	(3)
Multirate Signal Processing	175	(66)
Decimation and Interpolation	175	(4)
Noble Identities	176	(2)
Sampling Rate Conversion by Rational Factor	178	(1)
Polyphase Decomposition	179	(8)
Recursive IIR Decimator	183	(1)
Fast-running FIR Filter	184	(3)
Hogenauer CIC Filters	187	(16)
Single-Stage CIC Case Study	187	(2)
Multistage CIC Filter Theory	189	(5)
Amplitude and Aliasing Distortion	194	(2)
Hogenauer Pruning Theory	196	(5)
CIC RNS Design	201	(2)
Multistage Decimator	203	(3)
Multistage Decimator Design Using Coodman--Carey Half-band Filters	204	(2)
Frequency-Sampling Filters as Bandpass Decimators	206	(4)
Filter Banks	210	(20)
Uniform DFT Filter Bank	210	(5)
Two-channel Filter Banks	215	(15)
Wavelets	230	(11)
The Discrete Wavelet Transformation	233	(4)
Exercises	237	(4)
Fourier Transforms	241	(48)
The Discrete Fourier Transform Algorithms	242	(17)
Fourier Transform Approximations Using the DFT	242	(2)
Properties of the DFT	244	(3)
The Goertzel Algorithm	247	(1)
The Bluestein Chirp-z Transform	248	(3)
The Rader Algorithm	251	(6)
The Winograd DFT Algorithm	257	(2)
The Fast Fourier Transform (FFT) Algorithms	259	(19)
The Cooley--Tukey FFT Algorithm	260	(10)
The Good--Thomas FFT Algorithm	270	(3)
The Winograd FFT Algorithm	273	(3)
Comparison of DFT and FFT Algorithms	276	(2)
Fourier-related Transforms	278	(11)
Computing the DCT Using the DFT	280	(1)
Fast Direct DCT Implementation	281	(2)
Exercises	283	(6)
Advanced Topics	289	(76)
Rectangular and Number Theoretic Transforms (NTTs)	289	(17)
Arithmetic Modulo 2b ± 1	291	(2)
Efficient Convolutions Using NTTs	293	(1)
Fast Convolution Using NTTs	294	(3)
Multidimensional Index Maps and the Agarwal--Burrus NTT	297	(2)
Computing the DFT Matrix with NTTs	299	(2)
Index Maps for NTTs	301	(4)
Using Rectangular Transforms to Compute the DFT	305	(1)
Error Control and Cryptography	306	(35)
Basic Concepts from Coding Theory	307	(5)
Block Codes	312	(4)
Convolutional Codes	316	(8)
Cryptography Algorithms for FPGAs	324	(17)
Modulation and Demodulation	341	(24)
Basic Modulation Concepts	341	(4)
Incoherent Demodulation	345	(6)
Coherent Demodulation	351	(9)
Exercises	360	(5)
Adaptive Filters	365	(58)
Application of Adaptive Filter	366	(2)
Interference Cancellation	366	(1)
Prediction	367	(1)
Inverse Modeling	367	(1)
Identification	368	(1)
Optimum Estimation Techniques	368	(6)
The Optimum Wiener Estimation	370	(4)
The Widrow--Hoff Least Mean Square Algorithms	374	(12)
Learning Curves	381	(2)
Normalized LMS (NLMS)	383	(3)
Transform Domain LMS Algorithms	386	(5)
Fast-convolution Techniques	386	(1)
Using Orthogonal Transforms	387	(4)
Implementation of the LMS Algorithm	391	(14)
Quantization Effects	391	(1)
FPGA Design of the LMS Algorithm	392	(3)
Pipelined LMS Filters	395	(3)
Transposed Form LMS Filter	398	(1)
Design of DLMS Algorithms	399	(3)
LMS Designs using Signum Function	402	(3)
Recursive Least Square Algorithms	405	(12)
RLS with Finite Memory	409	(2)
Fast RLS Kalman Implementation	411	(5)
The Fast a Posteriori Kalman RLS Algorithm	416	(1)
Comparison of LMS and RLS Parameters	417	(6)
Exercises	419	(4)
References	423	(12)
A. Verilog Source Code	435	(52)
B. VHDL and Verilog Coding	487	(22)
List of Examples	489	(1)
Library of Parameterized Modules (LPM)	490	(19)
The Parameterized Flip-flop Megafunction (1pm_ff)	490	(4)
The Parameterized Adder/Subtractor Megafunction (1pm_add_sub)	494	(5)
The Parameterized Multiplier Megafunction (lpm_mult)	499	(4)
The Parameterized ROM Megafunction (1pm_rom)	503	(3)
The Parameterized Divider Megafunction (lpm_divide)	506	(3)
C. Glossary	509	(14)
D. CD-ROM File: ``1readme.ps''	515	(8)
Index	523