Digital System Design using FSMs A Practical Learning Approach

by Minns, Peter D.

• ISBN13: 9781119782704
• ISBN10: 1119782708
• eBook ISBN(s): 9781119782728
• Edition: 1st
• Format: Hardcover
• Copyright: 2021-06-28
• Publisher: Wiley
• More Book Details
• Purchase Benefits

Summary

DIGITAL SYSTEM DESIGN USING FSMS

Explore this concise guide perfect for digital designers and students of electronic engineering who work in or study embedded systems

Digital System Design using FSMs: A Practical Learning Approach delivers a thorough update on the author’s earlier work, FSM-Based Digital Design using Verilog HDL. The new book retains the foundational content from the first book while including refreshed content to cover the design of Finite State Machines delivered in a linear programmed learning format. The author describes a different form of State Machines based on Toggle Flip Flops and Data Flip Flops.

The book includes many figures of which 15 are Verilog HDL simulations that readers can use to test out the design methods described in the book, as well as 19 Logisim simulation files with figures. Additional circuits are also contained within the Wiley web folder. It has tutorials and exercises, including comprehensive coverage of real-world examples demonstrated alongside the frame-by-frame presentations of the techniques used.

In addition to covering the necessary Boolean algebra in sufficient detail for the reader to implement the FSM based systems used in the book, readers will also benefit from the inclusion of:

• A thorough introduction to finite-state machines and state diagrams for the design of electronic circuits and systems
• An exploration of using state diagrams to control external hardware subsystems
• Discussions of synthesizing hardware from a state diagram, synchronous and asynchronous finite-state machine designs, and testing finite-state machines using a test-bench module
• A treatment of the One Hot Technique in finite-state machine design
• An examination of Verilog HDL, including its elements
• An analysis of Petri-Nets including both sequential and parallel system design

Suitable for design engineers and senior technicians seeking to enhance their skills in developing digital systems, Digital System Design using FSMs: A Practical Learning Approach will also earn a place in the libraries of undergraduate and graduate electrical and electronic engineering students and researchers.

Author Biography

Dr Peter D. Minns, Formally Senior Lecturer in the Department of Mathematics, Physics and Electrical Engineering at Northumbria University at Newcastle. Now retired, Dr Minns worked as an academic Senior Lecturer for some 33 years in which he taught FSM and Digital Electronics, and computer programming with microprocessors and microcontrollers. Prior to academia, he worked in the telecommunications industry, then in Power System Protection as a Design and Development Engineer at many levels including relay logic, TTL, CMOS, FPGA. Whilst working at the University he was also involved with Knowledge Based Learning with Knowledge Transfer Partnerships (KTP) between the University and Industry.

Table of Contents

Preface

Acknowledgements

About the Companion Website

1             Introduction to Finite State Machines

               1.1         Some Notes on Style

2             Using FSMs to Control External Devices

               2.1         Introduction

3             Introduction to FSM Synthesis

3.1         Introduction

3.2         Tutorials Covering Chapters 1, 2, and 3

3.2.1      Binary data serial transmitter FSM

3.2.2      The high low FSM system

3.2.3      The clocked watchdog timer FSM

3.2.4      The asynchronous receiver system clocked FSM

4             Asynchronous FSM Methods

4.1         Introduction to Asynchronous FSM

4.2         Summary

4.3         Tutorials

4.3.1      FSM motor with fault detection

4.3.2      The mower in four and two states

5             Clocked One Hot Method of FSM Design

5.1         Introduction

5.2         Tutorials on the Clocked One Hot FSM Method

5.2.1      Seven-state system clocked one hot method

5.2.2      Memory tester FSM

5.2.3      Eight-bit sequence detector FSM

6             Further Event-Driven FSM Design

6.1         Introduction

6.2         Conclusions

7             Petri Net FSM Design

7.1         Introduction

7.2         Tutorials Using Petri Net FSM

7.2.1      Controlled shared resource Petri nets

7.2.2      Serial clock-driven Petri net FSM

7.2.3      Using asynchronous (event driven) design with Petri nets

7.3         Conclusions

Appendix A1:     Boolean Algebra

A1.1       Basic Gate Symbols

A1.2       The Exclusive OR and Exclusive NOR

A1.3       Laws of Boolean Algebra

A1.3.1   Basic OR rules

A1.3.2   Basic AND rules

A1.3.3   Associative and commutative laws

A1.3.4   Distributive laws

A1.3.5   Auxiliary rule for static 1 hazard removal

A1.3.6   Consensus theorem

A1.3.7   The effect of signal delay in logic gates

A1.3.8   De-Morgan’s theorem

A1.4       Examples of Applying the Laws of Boolean Algebra

A1.4.1   Converting AND–OR to NAND

A1.4.2   Converting AND–OR to NOR

A1.4.3   Logical adjacency rule

A1.5       Summary

Appendix A2: Use of Verilog HDL and Logisim to FSM

A2.1       The Single-Pulse Generator with Memory Clock-Driven FSM

A2.2       Test Bench Module and Its Purpose

A2.3       Using SynaptiCAD Software

A2.4       More Direct Method

A2.5       A Very Simple Guide to Using the Logisim Simulator

A2.5.1   The Logisim top level menu items

A2.6       Using Flip-Flops in a Circuit

A2.7       Example Single-Pulse FSM

A2.8       How to Use the Simulator to Simulate the Single-Pulse FSM

A2.8.1   Using Logisim with the truth table approach

A2.9       Using Logisim with the Truth Table Approach

A2.9.1   Useful note

A2.10     Summary

Appendix A3: Counters, Shift Registers, Input, and Output with an FSM

A3.1       Basic Down Synchronous Binary Counter Development

A3.2       Example of a Four-Bit Synchronous Up Counter with T Type Flip-Flops

A3.3       Parallel Loading Counters – Using T Flip-Flops

A3.4       Using D Flip-Flops to Build Parallel Loading Counters

A3.5       Simple Binary Up Counter with Parallel Inputs

A3.6       Clock Circuit to Drive the Counter (and FSM)

A3.7       Counter Design Using Don’t Care States

A3.8       Shift Registers

A3.9       Dealing with Input and Output Signals Using FSM

A3.10     Using Logisim to Work with Larger FSM Systems

A3.10.1 The Equations

A3.11     Summary

Appendix A4: Finite State Machines Using Verilog Behavioural Mode

A4.1       Introduction

A4.2       The Single-Pulse/Multiple-Pulse Generator with Memory FSM

A4.3       The Memory Tester FSM Revisited

A4.4       Summary

Appendix A5:     Programming a Finite State Machine

A5.1       Introduction

A5.2       The Parallel Loading Counter

A5.3       The Multiplexer

A5.4       The Micro Instruction

A5.5       The Memory

A5.6       The Instruction Set

A5.7       Simple Example: Single-Pulse FSM

A5.8       The Final Example

A5.9       The Program Code

A5.10     Returning Unused States Via Other Transition Paths

A5.11     Summary

Appendix A6:     The Rotational Detector Using Logisim Simulator with Sub-Circuits

A6.1       Using the Two-State Diagram Arrangement

 

Bibliography

Index