Digital VLSI Chip Design with Cadence and Synopsys CAD Tools

by Brunvand, Erik

• ISBN13: 9780321547996
• ISBN10: 0321547993
• Edition: 1st
• Format: Paperback
• Copyright: 2009-02-25
• Publisher: Pearson

Summary

KEY BENEFIT : This hands-on book leads readers through the complete process of building a ready-to-fabricate CMOS integrated circuit using popular commercial design software. KEY TOPICS : The VLSI CAD flow described in this book uses tools from two vendors: Cadence Design Systems, Inc. and Synopsys Inc. Detailed tutorials include step-by-step instructions and screen shots of tool windows and dialog boxes. MARKET : A useful reference for chip designers.

Author Biography

Professor Erik Brunvand is an associate professor in the School of Computing at the University of Utah. He has interests in computer architecture and VLSI systems in general, and self-timed and asynchronous systems in particular. One aspect of his research involves compiling concurrent communicating programs into asynchronous VLSI circuits. The current system allows programs written in a subset of occam, a concurrent message-passing programming language based on CSP, to be automatically compiled into a set of self-timed circuit modules suitable for manufacture as an integrated circuit. He is also interested in investigating the effects of asynchrony on computer systems architecture at a higher level. To explore these ideas he is building a series of prototype asynchronous computer systems out of FPGA and custom VLSI chips.

Table of Contents

Introduction	p. 1
CAD Tool Flows	p. 2
Custom VLSI and Cell Design Flow	p. 3
Hierarchical Cell/Block ASIC Flow	p. 3
What This Book Is and Isn't	p. 4
Bugs in the Tools?	p. 5
Tool Setup and Execution Scripts	p. 6
Typographical Conventions	p. 7
Cadence DFII and ICFB	p. 9
Cadence Design Framework	p. 9
Starting Cadence	p. 11
Summary	p. 16
Composer Schematic Capture	p. 17
Starting Cadence and Making a New Working Library	p. 18
Creating a New Cell	p. 19
Creating the Schematic View of a Full Adder	p. 19
Creating the Symbol View of a Full Adder	p. 26
Creating a Two-Bit Adder Using the FullAdder Bit	p. 28
Schematics that Use Transistors	p. 31
Printing Schematics	p. 33
Modifying PostScript Plot Files	p. 38
Variable, Pin, and Cell Naming Restrictions	p. 39
Summary	p. 40
Verilog Simulation	p. 41
Verilog Simulation of Composer Schematics	p. 44
Verilog-XL: Simulating a Schematic	p. 45
NC Verilog: Simulating a Schematic	p. 65
Behavioral Verilog Code in Composer	p. 69
Generating a Behavioral View	p. 72
Simulating a Behavioral View	p. 75
Stand-Alone Verilog Simulation	p. 76
Verilog-XL	p. 78
NC Verilog	p. 80
VCS	p. 87
Timing in Verilog Simulations	p. 90
Behavioral Versus Transistor Switch Simulation	p. 94
Behavioral Gate Timing	p. 96
Standard Delay Format (SDF) Timing	p. 99
Transistor Timing	p. 101
Summary	p. 107
Virtuoso Layout Editor	p. 109
An Inverter Schematic	p. 111
Starting Cadence icfb	p. 111
Making an Inverter Schematic	p. 111
Making an Inverter Symbol	p. 112
Layout for an Inverter	p. 113
Creating a New layout View	p. 113
Drawing an nmos Transistor	p. 113
Drawing a pmos Transistor	p. 118
Assembling the Inverter from the Transistor Layouts	p. 122
Using Hierarchy in Layout	p. 128
Virtuoso Command Overview	p. 130
Printing Layouts	p. 134
Design Rule Checking	p. 134
DIVA Design Rule Checking	p. 134
Generating an Extracted View	p. 140
Layout Versus Schematic Checking (LVS)	p. 141
Generating an analog-extracted View	p. 152
Overall Cell Design Flow (So Far.)	p. 153
Summary	p. 153
Standard Cell Design Template	p. 155
Standard Cell Geometry Specification	p. 156
Standard Cell I/O Pin Placement	p. 158
Standard Cell Transistor Sizing	p. 161
Summary	p. 162
Spectre Analog Simulator	p. 167
Simulating a Schematic (Transient Simulation)	p. 169
Simulation with the Spectre Analog Environment	p. 171
Simulating with a Config View	p. 176
Mixed Analog/Digital Simulation	p. 182
Final Words about Mixed-Mode Simulation	p. 194
DC Simulation	p. 198
Parametric Simulation	p. 204
Power Measurements	p. 205
Summary	p. 213
Cell Characterization	p. 215
Liberty File Format	p. 215
Combinational Cell Definition	p. 219
Sequential Cell Definition	p. 221
Tristate Cell Definition	p. 228
Cell Characterization with ELC	p. 230
Generating the ELC Netlist	p. 230
Cell Naming and Encounter Library Characterizer	p. 243
Best, Typical, and Worst Case Characterization	p. 244
Cell Characterization with Spectre	p. 244
Converting Liberty to Synopsys Database (db) Format	p. 250
Summary	p. 252
Verilog Synthesis	p. 253
Synopsys Design Compiler Synthesis with dc shell	p. 253
Basic Synthesis	p. 254
Scripted Synthesis	p. 258
Synopsys Design Vision GUI	p. 267
DesignWare Building Blocks	p. 276
Cadence RTL Compiler Synthesis	p. 277
Scripted Synthesis	p. 277
Cadence RTL Compiler GUI	p. 280
Importing Structural Verilog into Cadence DFII	p. 285
Post-Synthesis Verilog Simulation	p. 288
Summary	p. 295
Abstract Generation	p. 299
Reading Your Library into Abstract	p. 300
Finding Pins in Your Cells	p. 303
The Extract Step	p. 306
The Abstract Step	p. 306
LEF File Generation	p. 306
Modifying the LEF File	p. 309
Summary	p. 311
SOC Encounter Place and Route	p. 313
Encounter GUI	p. 315
Reading In the Design	p. 318
Floorplanning	p. 323
Power Planning	p. 327
Placing the Standard Cells	p. 333
First Optimization Phase	p. 333
Clock Tree Synthesis	p. 336
Post-CTS Optimization	p. 338
Final Routing	p. 338
Post-Route Optimization	p. 343
Adding Filler Cells	p. 345
Checking the Result	p. 345
Saving and Exporting the Placed and Routed Cell	p. 349
Reading the Cell Back into Virtuoso	p. 352
Design Import with Configuration Files	p. 358
Floorplanning	p. 361
SOC Encounter Scripting	p. 361
Summary	p. 364
Chip Assembly	p. 367
Module Routing with ccar	p. 367
Preparing a Placement with Virtuoso-XL	p. 369
Invoking the ccar Router	p. 374
Core to Pad Frame Routing with ccar	p. 382
Copy the Pad Frame	p. 383
Modify the Frame schematic View	p. 385
Modify the Frame layout View	p. 390
Routing the Core to Frame with ccar	p. 391
Metal Density Issues	p. 399
Final GDSII Generation	p. 399
Summary	p. 405
Design Example	p. 409
Tiny MIPS	p. 410
Tiny MIPS: Flat Tool Flow	p. 416
Synthesis	p. 416
Place and Route	p. 420
Simulation	p. 432
Final Assembly	p. 443
Tiny MIPS: Hierarchical Tool Flow	p. 446
Synthesis	p. 449
Place and Route into a Macro Block	p. 449
Preparing Custom Circuits for Hierarchy	p. 451
Generating Abstract Views for Blocks	p. 454
Place and Route with Macro Blocks	p. 456
Simulation	p. 470
Final Assembly	p. 470
Summary	p. 470
Tool and Setup Scripts	p. 475
Cadence Tool Installation	p. 476
Cadence Setup Scripts	p. 478
setup-cadence: Basic Cadence Setup	p. 478
setup-ncsu: Cadence Setup with NCSU Extensions	p. 481
Shell Scripts for Cadence Tools	p. 482
syn-abstract: Start the Abstract Tool	p. 482
cad-alf2lib: Convert the alf Notation from Encounter Library Characterizer to lib Notation	p. 482
cad-elc: Start the Encounter Library Characterizer	p. 483
cad-ncsu: Start the DFII (icfb) Environment	p. 484
cad-soc: Start the SOC Encounter Place and Route Tool	p. 484
sim-ncg: Startup Script for the NC Verilog Simulator, with GUI	p. 485
sim-xlg: Startup Script for the Verilog-XL simulator, with GUI	p. 485
sptr2elc: Perl Script for Converting Spectre Netlists to Encounter Library Characterizer Netlists
syn-rtlg: Start the RTL Compiler Synthesis Tool, with GUI	p. 487
Synopsys Tool Installation	p. 488
Synopsys Setup Scripts	p. 489
setup-synopsys: Basic Synopsys Setup	p. 489
Shell Scripts for Synopsys Tools	p. 492
sim-vcs: Startup Script for the VCS Verilog Simulator	p. 492
sim-simv: Startup Script for the simv Simulator Resulting from VCS Execution	p. 493
syn-dc: Startup Script for Design Compiler Synthesis	p. 494
syn-dv: Startup Script for Design Compiler using the Design Vision GUI	p. 494
Summary	p. 495
Scripts to Drive the Tools	p. 497
Tcl Script Basics	p. 497
Cadence Tool Scripts	p. 499
Encounter Library Characterizer Cell Characterization	p. 500
Cell Characterization with Spectre	p. 504
SOC Encounter Place and Route	p. 509
RTL Compiler Synthesis	p. 516
ccar Chip Assembly Tool	p. 517
Synopsys Tool Scripts	p. 519
Synopsys Design Compiler Script Files	p. 519
Summary	p. 524
Technology and Cell Libraries	p. 525
NCSU Cadence Design Kit CDK1.5 Installation	p. 525
cdsinit: Local Modifications	p. 526
cdsenv: Local Modifications	p. 529
UofU TechLib ami06: Local Modifications	p. 530
Example Standard Cells	p. 535
Example Liberty File	p. 536
LEF File Technology Header	p. 551
LEF File MACRO Examples	p. 554
Summary	p. 563
Bibliography	p. 565
Index	p. 567
Table of Contents provided by Publisher. All Rights Reserved.