DRAM Circuit Design Fundamental and High-Speed Topics

by Keeth, Brent; Baker, R. Jacob; Johnson, Brian; Lin, Feng

• ISBN13: 9780470184752
• ISBN10: 0470184752
• Edition: 2nd
• Format: Hardcover
• Copyright: 2007-12-04
• Publisher: Wiley-IEEE Press

Summary

This easy-to-read tutorial focuses on the chip designer rather than the user. It covers the transistor-level design of DRAM building blocks, including architecture and the array, voltage regulators and pumps, and peripheral circuits. This book presents both standard and high-speed implementations in a balanced approach to help IC designers prepare for the future. It includes details of delay-locked loops (DLLs), digital phase-locked loops (DPLLs), output circuit paths including transmission lines, terminations, and protocols.

Author Biography

Brent Keeth is a Fellow in DRAM Design R&D at Micron Technology, Inc. His twenty-five years of industry experience spans radar systems, avionics components, communicationsystems, professional production and post-production equipment for the broadcast television industry, and solid-state memory. He holds over 400 U.S. and foreign granted or pending patents.

R. Jacob Baker, PhD, is an engineer, educator, and inventor. He has more than twenty years of engineering experience and holds over 200 granted or pending patents in integrated circuit design. Dr. Baker is the author of several circuit design books. For a detailed biography, see http://cmosedu.com/jbaker/jbaker.htm.

Brian Johnson is a Senior Design Engineer in DRAM Design R&D at Micron Technology, Inc. His research interests include asynchronous sequential circuits, clock synchronization circuits, and high-speed logic design. He holds over 60 granted or pending patents related to DRAM design and integrated circuit design.

Feng Lin, PhD, is a Senior Design Engineer in DRAM Design R&D at Micron Technology, Inc. His research interests include high-speed I/O circuits, PLL/DLL, and mixed-signal circuit design. Dr. Lin holds over 50 granted or pending patents related to DRAM and integrated circuit design.

Table of Contents

Preface	p. xi
An Introduction to DRAM
DRAM Types and Operation	p. 1
The 1k DRAM (First Generation)	p. 1
The 4k-64 Meg DRAM (Second Generation)	p. 7
Synchronous DRAM (Third Generation)	p. 15
DRAM Basics	p. 22
Access and Sense Operations	p. 24
Write Operation	p. 28
Opening a Row (Summary)	p. 29
Open/Folded DRAM Array Architectures	p. 31
The DRAM Array
The Mbit Cell	p. 33
The Sense Amp	p. 44
Equilibration and Bias Circuits	p. 44
Isolation Devices	p. 46
Input/Output Transistors	p. 46
Nsense and Psense Amplifiers	p. 47
Rate of Activation	p. 49
Configurations	p. 49
Operation	p. 52
Row Decoder Elements	p. 54
Bootstrap Wordline Driver	p. 55
NOR Driver	p. 57
CMOS Driver	p. 58
Address Decode Tree	p. 58
Static Tree	p. 59
P&E Tree	p. 59
Predecoding	p. 60
Pass Transistor Tree	p. 61
Discussion	p. 61
Array Architectures
Array Architectures	p. 65
Open Digitline Array Architecture	p. 65
Folded Array Architecture	p. 75
Design Examples: Advanced Bilevel DRAM Architecture	p. 83
Array Architecture Objectives	p. 84
Bilevel Digitline Construction	p. 85
Bilevel Digitline Array Architecture	p. 68
Architectural Comparison	p. 93
The Peripheral Circuitry
Column Decoder Elements	p. 99
Column and Row Redundancy	p. 102
Row Redundancy	p. 104
Column Redundancy	p. 107
Global Circuitry and Considerations
Data Path Elements	p. 111
Data Input Buffer	p. 111
Data Write Muxes	p. 115
Write Driver Circuit	p. 116
Data Read Path	p. 118
DC Sense Amplifier (DCSA)	p. 119
Helper Flip-Flop (HFF)	p. 121
Data Read Muxes	p. 122
Output Buffer Circuit	p. 124
Test Modes	p. 125
Address Path Elements	p. 126
Row Address Path	p. 126
Row Address Buffer	p. 127
CBR Counter	p. 127
Predecode Logic	p. 128
Refresh Rate	p. 128
Array Buffers	p. 130
Phase Drivers	p. 131
Column Address Path	p. 131
Address Transition Detection	p. 132
Synchronization in DRAMs	p. 135
The Phase Detector	p. 137
The Basic Delay Element	p. 137
Control of the Shift Register	p. 138
Phase Detector Operation	p. 139
Experimental Results	p. 140
Discussion	p. 142
Voltage Converters
Internal Voltage Regulators	p. 147
Voltage Converters	p. 147
Voltage References	p. 148
Bandgap Reference	p. 153
The Power Stage	p. 154
Pumps and Generators	p. 158
Pumps	p. 158
DVC2 Generator	p. 165
Discussion	p. 165
An Introduction to High-Speed DRAM
The Performance Paradigm	p. 167
Performance for DRAM Memory Devices	p. 169
Underlying Technology Improvements	p. 171
High-Speed Die Architectures
Introduction: Optimizing DRAM Architecture for High Performance	p. 173
Architectural Features: Bandwidth, Latency, and Cycle Time	p. 175
Architectural Limiters: The Array Data Path	p. 176
Architectural Limiters: The Read Data Path	p. 183
Architectural Limiters: Latency	p. 186
Conclusion: Designing for High Performance	p. 190
Input Circuit Paths
Introduction	p. 193
Input Receivers	p. 196
Matched Routing	p. 200
Capture Latches	p. 203
Input Timing Adjustments	p. 206
Current Mode Logic (CML)	p. 212
Output Circuit Paths
Transmission Line, Impedance, and Termination	p. 220
Impedance Control	p. 224
Simultaneous Switching Noise (SSN)	p. 230
Signal Return Path Shift (SRPS)	p. 238
Electrostatic Discharge (ESD)	p. 242
Parallel-to-Serial Conversion	p. 244
Emerging Memory I/O Features	p. 248
Timing Circuits
Introduction	p. 251
All-Digital Clock Synchronization Design	p. 254
Timing Analysts	p. 255
Digital Delay Line	p. 259
Phase Detector (PD)	p. 267
Test and Debug	p. 273
Dual-Loop Architecture	p. 274
Mixed-Mode Clock Synchronization Design	p. 275
Analog Delay Line	p. 276
Charge-Pump Phase Detector (CPPD)	p. 283
Dual-Loop Analog DLL	p. 286
Mixed-Mode DLL and Its Applications	p. 289
What's Next for Timing	p. 291
Control Logic Design
Introduction	p. 295
DRAM Logic Styles	p. 298
Process Limitations	p. 298
Array Operation	p. 301
Performance Requirements	p. 304
Delay-Chain Logic Style	p. 306
Domino Logic	p. 309
Testability	p. 314
Command and Address Control	p. 317
Command Decoder	p. 318
Read and Write Data Address Registers	p. 324
Column Access Control	p. 328
Write Data Latency Timing and Data Demultiplexing	p. 330
Write Latency Timing	p. 332
Write Data Demultiplexing	p. 338
Read Data Latency Timing and Data Multiplexing	p. 346
Read Data FIFO	p. 350
Read Latency (CL) Tracking	p. 359
Comments on Future Direction for DRAM Logic Design	p. 367
Power Delivery
Power Delivery Network Design	p. 373
Device/Package Co-design	p. 376
Full-Chip Simulations	p. 380
Future Work in High-Performance Memory	p. 385
Appendix	p. 391
Glossary	p. 407
Index	p. 413
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