Electronic Chips & Systems Design Languages

by Mermet, Jean

• ISBN13: 9780792373117
• ISBN10: 0792373111
• Format: Hardcover
• Copyright: 2001-04-01
• Publisher: Kluwer Academic Pub

Summary

Electronic Chips & Systems Design Languagesoutlines and describes the latest advances in design languages. The challenge of System on a Chip (SOC) design requires designers to work in a multi-lingual environment which is becoming increasingly difficult to master. It is therefore crucial for them to learn, almost in real time, from the experiences of their colleagues in the use of design languages and how these languages have become more advanced to cope with system design. System designers, as well as students willing to become system designers, often do not have the time to attend all scientific events where they could learn the necessary information. This book will bring them a selected digest of the best contributions and industry strength case studies. All the levels of abstraction that are relevant, from the informal user requirements down to the implementation specifications, are addressed by different contributors. The author, together with colleague authors who provide valuable additional experience, presents examples of actual industrial world applications. Furthermore the academic concepts presented in this book provide excellent theories to student readers and the concepts described are up to date and in so doing provide most suitable root information for Ph.D. postgraduates.

Table of Contents

Contributors	viii
Preface	ix
VHDL EXTENSIONS	1	(84)
VHDL-AMS-Introduction	2	(3)
Alain Vachoux
Library Development Using the VHDL-AMS Language	5	(12)
E. Christen
K. Bakalar
Behavioral Modeling of Complex Heterogeneous Microsystems	17	(14)
P. Schwarz
J. Haase
VHDL-AMS, a Unified Language to Describe Multi-Domain, Mixed-Signal Designs. Mechatronic Applications	31	(12)
V. Aubert
S. Garcia-Sabiro
Efficient Modeling of Analog and Mixed A/D Systems via Piece-Wise Linear Technique	43	(14)
J. Dabrowski
A. Pulka
OO-VHDL	55	(2)
SUAVE: Object-Oriented and Genericity Extensions to VHDL for High-Level Modeling	57	(14)
P. Ashenden
P. Wilsey
D. Martin
Digital Circuit Design with Objective VHDL	71	(14)
M. Radetzki
W. Nebel
SYSTEM LEVEL DESIGN	85	(140)
HW/SW Co-design	87	(2)
UF: Architecture and Semantics for System-Level Multiformalism Descriptions	89	(10)
L. S. Fernandez
N. Martinez
S. Pickin
A. Groba
A. Alonso
Automatic Interface Generation among VHDL Processes in HW/SW Co-Design	99	(12)
E. Barros
C. de Araujo
System-Level Specification and Architecture Exploration: An Avionics Codesign Application	111	(10)
F. Cloute
J.N. Contensou
D. Esteve
P. Pampagnin
P. Hons
Y. Favard
Using SDL to Model Reactive Embedded System in a Co-design Environment	121	(10)
R. Kumar
A Synchronous Object-Oriented Design Flow for Embedded Applications	131	(14)
P.G. Ploger
R. Budde
K.H. Sylla
Co-simulation	143	(2)
Heterogeneous System-Level Cosimulation with SDL and Matlab	145	(14)
P. Bjureus
A. Jantsch
VHDL-Based HW/SW Cosimulation of Microsystems	159	(10)
V. Moser
A. Boegli
H.P. Amann
F. Pellandini
Modeling Interrupts for HW/SW Co-Simulation Based on VHDL/C Coupling	169	(12)
M. Bauer
W. Ecker
A. Zinn
SLD methodology	179	(2)
A Comparison of Six Languages for System Level Description of Telecom Applications	181	(12)
A. Jantsch
S. Kumar
I. Sander
B. Svantesson
J. Oberg
A. Hemani
P. Ellervee
M. O'Nils
High Level Modelling in SDL and VHDL+	193	(12)
F. Cook
A. Carpenter
N. Messer
ECL: A Specification Environment for System-Level Design	205	(8)
E. Sentovich
G. Berry
E. Harcourt
L. Lavagno
The MCSE Approach for System-Level Design	213	(12)
J.P. Calvez
O. Pasquier
F. Muller
D. Heller
E. Chenard
SYNTHESIS	225	(36)
Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement	227	(12)
D. Sciuto
D. Corvino
I. Epicoco
F. Ferrandi
F. Fummi
VHDL Dynamic Loop Synthesis	239	(10)
M.F. Albenge
D. Houzet
Hierarchical Module Expansion in a VHDL Behavioural Synthesis System	249	(12)
A.D. Brown
A.C. Williams
Z.A. Baidas
FORMAL VERIFICATION	261	(2)
Formal Verification
Port-Stitching: An Interface-Oriented Hardware Specification and VHDL Model Generation	263	(10)
A.F. Nicolae
E. Cerny
Formal Verification of VHDL using VHDL-Like ACL2 Models	273	(12)
D. Borrione
P. Georgelin
Specification of Embedded Monitors for Property Checking	285	(10)
M. Bombana
A. Allara
S. Comai
B. Josko
R. Schlor
D. Sciuto
Formal Specification and Verification of Transfer-Protocols for System-Design in VHDL	295
O. Drogehorn
H.D. Hummer
W. Geisselhardt