Beachnote | |
Can They Be Fixed: Some Thoughts After 40 Years in the Business | p. 1 |
Architecture | |
On the Benefit of Caching Traffic Flow Data in the Link Buffer | p. 2 |
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor | p. 12 |
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic | p. 23 |
Scalable Architecture for Prefix Preserving Anonymization of IP Addresses | p. 33 |
New Frontiers | |
Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology | p. 43 |
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications | p. 53 |
802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec | p. 65 |
SoC | |
A Real-Time Programming Model for Heterogeneous MPSoCs | p. 75 |
A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation | p. 85 |
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs | p. 96 |
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors | p. 106 |
Application Specific | |
Area Reliability Trade-Off in Improved Reed Muller Coding | p. 116 |
Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set | p. 126 |
ASIP-eFPGA Architecture for Multioperable GNSS Receivers | p. 136 |
Special Session: System Level Design for Heterogeneous Systems | |
Introduction to System Level Design for Heterogeneous Systems | p. 146 |
Streaming Systems in FPGAs | p. 147 |
Heterogeneous Design in Functional DIF | p. 157 |
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study | p. 167 |
Evaluation of ASIPs Design with LISATek | p. 177 |
High Level Loop Transformations for Systematic Signal Processing Embedded Applications | p. 187 |
Memory-Centric Hardware Synthesis from Dataflow Models | p. 197 |
Special Session: Programming Multicores | |
Introduction to Programming Multicores | p. 207 |
Design Issues in Parallel Array Languages for Shared Memory | p. 208 |
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency | p. 218 |
Sensors and Sensor Networks | |
Climate and Biological Sensor Network | p. 229 |
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors | p. 238 |
Application Server for Wireless Sensor Networks | p. 248 |
Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks | p. 258 |
System Modeling and Design | |
Signature-Based Calibration of Analytical System-Level Performance Models | p. 268 |
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures | p. 279 |
Intellectual Property Protection for Embedded Sensor Nodes | p. 289 |
Author Index | p. 299 |
Table of Contents provided by Blackwell. All Rights Reserved. |
The New copy of this book will include any supplemental materials advertised. Please check the title of the book to determine if it should include any access cards, study guides, lab manuals, CDs, etc.
The Used, Rental and eBook copies of this book are not guaranteed to include any supplemental materials. Typically, only the book itself is included. This is true even if the title states it includes any access cards, study guides, lab manuals, CDs, etc.