ESD Failure Mechanisms and Models

by Voldman, Steven H.

• ISBN13: 9780470511374
• ISBN10: 0470511370
• Edition: 1st
• Format: Hardcover
• Copyright: 2009-08-17
• Publisher: Wiley

Summary

This book presents information on electrostatic discharge (ESD) failure mechanisms, spanning a range of technologies from early CMOS applications to future CMOS concepts. Voldman uses his wealth of experience in the field of ESD to address failure mechanisms associated with each CMOS generation, including those applicable to electrical overstress (EOS) and latchup. He also provides the processes or circuit solutions for eliminating failure defects, giving practical examples of failure mechanisms and the working applications they can effect. The book opens with an exposition of the historical trends behind ESD, including how technology scaling has affected the ESD failure mechanisms, and potential developments of the technology. The book goes on to examine different failure models and analysis tools, before applying this to CMOS technology; past, present and future developments, SOI technology, RF CMOS and RF MEMS. The final chapters of the book cover bipolar technology failures, Gallium Arsenide failure mechanisms and devices and magnetic recording failure mechanisms. Provides a comprehensive analysis of ESD failure mechanisms over a wide range of semiconductor materials, devices, circuits and applications. Sets out methods for eliminating failure mechanisms through workable circuit solutions, including practical examples of failure defects. Discusses established and contemporary technologies, as well as emerging and future trends such as RF complementary metal-oxide semiconductor (CMOS) and digital applications, carbon nanotubes (CNTs), local oxidization of silicon (LOCOS)-based CMOS, STI-based CMOS, multi-gate devices (MUGFETs) and FinFET transistors. Addresses the historical trends in ESD failure mechanisms, including how ESD failure practice is used to design and improve semiconductor chips, and how technology scaling has affected this.

Author Biography

Dr Steven H. Voldman received his B.S. in Engineering Science from the University of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from M.I.T; MS Engineering Physics (1986) and Ph.D EE (1991) from the University of Vermont under IBM's Resident Study Fellow Program. At M.I.T, he worked as a member of the M.I.T. Plasma Fusion Center, and the High Voltage Research Laboratory (HVRL). At IBM, as a reliability device engineer, his work include pioneering work in bipolar/ CMOS SRAM alpha particle and cosmic ray SER simulation, MOSFET gate-induced drain leakage (GIDL) mechanism, hot electron, epitaxy/well design, CMOS latchup, and ESD. Since 1986, he has been responsible for defining the IBM ESD/latchup strategy for CMOS, SOI, BiCMOS and RF CMOS and SiGe technologies. He has authored ESD and latchup publications in the area of MOSFET Scaling, device simulations, copper, low-k, MR heads, CMOS, SOI , Sage and SiGeC technology. Voldman served as SEMATECH ESD Working Group Chairman (1996-2000), ESD Association General Chairman and Board of Directors, International Reliability Physics (IRPS) ESD/Latchup Chairman, International Physical and Failure Analysis (IPFA) Symposium ESD Sub-Committee Chairman, ESD Association Standard Development Chairman on Transmission Line Pulse Testing, ESD Education Committee, and serves on the ISQED Committee, Taiwan ED Conference (T-ESDC) Technical Program Committee. Voldman has provided ESD lectures for universities (e.g. MIT Lecture Series, Taiwan National Chiao-Tung University, and Singapore Nanyang Technical University). He is a recipient of over 125 US patents, over 100 publications, and also provides talks on patenting, and invention. He has been featured in EE Times, Intellectual Property Law and Business and authored the first article on ESD phenomena for the October 2002 edition of Scientific American entitled Lightening Rods for Nanostructures, and Pour La Science, Le Scienze, and Swiat Nauk international editions. Dr. Voldman was recently accepted as the first IEEE Fellow for ESD phenomena in semiconductors for ' contributions to electrostatic discharge protection CMOS, SOI and SiGe technologies'.

Table of Contents

About the Author

Preface

Acknowledgments

Failure Analysis and ESD

Introduction

ESD Failure: How Do Micro-electronic Devices Fail?

Sensitivity of Semiconductor Components

How Do Semiconductor Chips Fail--Are the Failures Random or Systematic?

Closing Comments and Summary

Problems

References

Failure Analysis Tools, Models, and Physics of Failure

FA Techniques for Evaluation of ESD Events

FA Tools

ESD Simulation: ESD Pulse Models

Electro-Thermal Physical Models

Statistical Models for ESD Prediction

Closing Comments and Summary

Problems

References

CMOS Failure Mechanisms

Tables of CMOS ESD Failure Mechanisms

LOCOS Isolation-Defined CMOS

Shallow Trench Isolation (STI)

Polysilicon-Defined Devices

Lateral Diode with Block Mask

MOSFETs

Resistors

Interconnects: Wires, Vias, and Contacts

ESD Failure in CMOS Nanostructures

Closing Comments and Summary

Problems

References

CMOS Circuits: Receivers and Off-Chip Drivers

Tables of CMOS Receiver and OCD ESD Failure Mechanisms

Receiver Circuits

Receivers Circuits with ESD Networks

Receiver Circuits with Half-Pass Transmission Gate

Receiver with Full-Pass Transmission Gate

Receiver, Half-Pass Transmission Gate, and Keeper Network

Receiver Circuit with Pseudo-zero V_T Half-Pass Transmission Gate

Receiver with Zero V_T Transmission Gate

Receiver Circuits with Bleed Transistors

Receiver Circuits with Test Functions

Receiver with Schmitt Trigger Feedback Networks

Off-Chip Drivers

Single NFET Pull-down OCD

Series Cascode MOSFETs

I/O Design Considerations and ESD Parasitic Failure Mechanisms

Closing Comments and Summary

Problems

References

CMOS Integration

Table of CMOS Integration ESD Failure Mechanisms

Architecture and Design Synthesis-Related Failures

Alternate Current Loop

Chip Capacitance

ESD Power Clamps

Intra- and Inter-domain ESD Protection

Split Ground Configurations

Mixed Voltage Interface

Mixed Signal Interface

Inter-domain Signal Line ESD Failures

Decoupling Capacitors

System Clock and Phase-Locked Loop

Fuse Networks

Bond Pads

MOSFET Gate Structure

Fill Shapes

No Connects

Test Circuitry

Multi-chip Systems

CMOS Latchup Failures

Closing Comments and Summary

Problems

References

SOI ESD Failure Mechanisms

Tables of SOI Device and Integration ESD Failure Mechanisms

SOI N-channel MOSFETs

SOI Diodes

SOI Buried Resistors

SOI Failure Mechanisms in 150 nm Technology

SOI ESD Failure Mechanisms in 45 nm Technology

SOI ESD Failure Mechanisms in 32 nm Technology

SOI ESD Failure Mechanisms in 22 nm Technology and the Future

SOI Design Synthesis and ESD Failure Mechanisms

SOI Integration: ESD Failure Mechanisms

Closing Comments and Summary

Problems

References

RF CMOS and ESD

Tables of RF CMOS ESD Failure Mechanisms

RF MOSFET

RF Shallow Trench Isolation Diode

RF Polysilicon Gated Diode

Silicon-Controlled Rectifier

Schottky Barrier Diodes

Capacitors

Resistors

Inductors

Examples of RF ESD Circuit Failure Mechanisms

Closing Comments and Summary

Problems

Reference

Micro-electromechanical Systems

Table of MEM Failure Mechanisms

Electrostatically Actuated Devices

Micro-mechanical Engines

Torsional Ratcheting Actuator

Electromagnetic Micro-power Generators

MEM Inductors

Electrostatically Actuated Variable Capacitor

Micro-mechanical Switches

RF MEM Switch

Micro-mechanical Mirrors

Electrostatically Actuated Torsional Micro-mirrors

Closing Comments and Summary

Problems

References

Gallium Arsenide

Tables of GaAs-Based ESD Failure Mechanisms

GaAs Technology

GaAs Energy-to-failure and Power-to-failure

GaAs ESD Failures in Active and Passive Elements

GaAs HBT Devices

GaAs HBT-Based Passive Elements

GaAs PHEMT Devices

GaAs Power Amplifiers

InGaAs

Gallium Nitride

InP and ESD

Closing Comments and Summary

Problems

References

Smart Power, LDMOS, and BCD Technology

Tables of LDMOS ESD Failure Mechanisms

LOCOS-Defined LDMOS Devices

STI-Defined LDMOS Devices

STI-Defined Isolated LDMOS Transistors

LDMOS Transistors: ESD Electrical Measurements

LDMOS-Based ESD Networks

LDMOS ESD Failure Mechanisms

LDMOS Transistor Design Enhancement

Latchup Events in LDMOS and BCD Technology

Closing Comments and Summary

Problems

References

Magnetic Recording

Tables of Magnetic Recording Failure Mechanisms

MR Heads

Inductive Heads

GMR Heads

TMR Heads

ESD Solutions

Closing Comments and Summary

Problems

References

Photo-masks and Reticles: Failure Mechanisms

Table of Photo-masks ESD Failure Mechanisms

Photo-mask Failure Mechanisms

Photo-mask Inspection Tools

Photo-mask ESD Characterization

Electrical Breakdown Versus Gap Spacing

Electrical Breakdown in Air: The Townsend Model

Electric Breakdown in Air: Toepler's Spark Law

Air Breakdown: The Paschen Breakdown Model

Paschen Curve Versus Reticle Breakdown Plot

Electrical Model of Photo-mask Breakdown

ESD Latent Damage

ESD Damage for Single Versus Multiple Events

ESD Damage to Anti-reflective Coating

ESD Solutions in Photo-masks

Closing Comments and Summary

Problems

References

Index

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