Fault-tolerance Techniques for Sram-based Fpgas

by Kastensmidt, Fernanda Lima; Carro, Luigi; Reis, Ricardo A. L.

• ISBN13: 9780387310688
• ISBN10: 0387310681
• Format: Hardcover
• Copyright: 2006-07-30
• Publisher: Springer Verlag

Summary

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.

Table of Contents

DEDICATION	v
AUTHORS	ix
PREFACE	xi
1. INTRODUCTION	1	(8)
2. RADIATION EFFECTS IN INTEGRATED CIRCUITS	9	(20)
2.1 RADIATION ENVIRONMENT OVERVIEW	9	(4)
2.2 RADIATION EFFECTS IN INTEGRATED CIRCUITS	13	(4)
2.2.1 SEU Classification	16	(1)
2.3 PECULIAR EFFECTS IN SRAM-BASED FPGAS	17	(12)
3. SINGLE EVENT UPSET (SEU) MITIGATION TECHNIQUES	29	(44)
3.1 DESIGN-BASED TECHNIQUES	31	(23)
3.1.1 Detection Techniques	32	(1)
3.1.2 Mitigation Techniques	33	(28)
3.1.2.1 Full Time and Hardware Redundancy	33	(6)
3.1.2.2 En-or Correction and Detection Codes	39	(4)
3.1.2.3 Hardened Memory Cells	43	(11)
3.2 EXAMPLES OF SEU MITIGATION TECHNIQUES IN ASICs	54	(7)
3.3 EXAMPLES OF SEU MITIGATION TECHNIQUES IN FPGAS	61	(22)
3.3.1 Antifuse based FPGAS	62	(3)
3.3.2 SRAM-based FPGAs	65	(33)
3.3.2.1 SEU Mitigation Solution in high-level description	66	(1)
3.3.2.2 SEU Mitigation Solutions at the Architectural level	67	(2)
3.3.2.3 Recovery technique	69	(4)
4. ARCHITECTURAL SEU MITIGATION TECHNIQUES	73	(10)
5. HIGH-LEVEL SEU MITIGATION TECHNIQUES	83	(8)
5.1 TRIPLE MODULAR REDUNDANCY TECHNIQUE FOR FPGAs	84	(4)
5.2 SCRUBBING	88	(3)
6. TRIPLE MODULAR REDUNDANCY (TMR) ROBUSTNESS	91	(20)
6.1 TEST DESIGN METHODOLOGY	95	(1)
6.2 FAULT INJECTION IN THE FPGA BITSTREAM	96	(2)
6.3 LOCATING THE UPSET IN THE DESIGN FLOORPLANNING	98	(5)
6.3.1 Bit column location in the matrix	99	(1)
6.3.2 Bit row location in the matrix	100	(1)
6.3.3 Bit location in the CLB	100	(1)
6.3.4 Bit Classification	101	(2)
6.4 FAULT INJECTION RESULTS	103	(5)
6.5 THE "GOLDEN" CHIP APPROACH	108	(3)
7. DESIGNING AND TESTING A TMR MICRO-CONTROLLER	111	(12)
7.1 AREA AND PERFORMANCE RESULTS	114	(2)
7.2 TMR 8051 MICRO-CONTROLLER RADIATION GROUND TEST RESULTS	116	(7)
8. REDUCING TMR OVERHEADS: PART I	123	(20)
8.1 DUPLICATION WITH COMPARISON COMBINED WITH TIME REDUNDANCY	124	(8)
8.2 FAULT INJECTION IN THE VHDL DESCRIPTION	132	(4)
8.3 AREA AND PERFORMANCE RESULTS	136	(7)
9. REDUCING TMR OVERHEADS: PART II	143	(28)
9.1 DWC-CED TECHNIQUE IN ARITHMETIC-BASED CIRCUITS	145	(23)
9.1.1 Using CED based on hardware redundancy	148	(2)
9.1.2 Using CED based on time redundancy	150	(2)
9.1.3 Choosing the most appropriated CED block	152	(2)
9.1.3.1 Multipliers	152	(1)
9.1.3.2 Arithmetic and Logic Unit (ALU)	153	(1)
9.1.3.3 Digital FIR Filter	154	(1)
9.1.4 Fault Coverage Results	154	(4)
9.1.4 Area and Performance Results	158	(10)
9.2 DESIGNING DWC-CED TECHNIQUE IN NON-ARITHMETIC-BASED CIRCUITS	168	(3)
10. FINAL REMARKS	171	(4)
REFERENCES	175