Field-Programmable Logic and Applications

by International Conference on Field-Programmable Logic and Applications (10th : 2000 : Villach, Austria); Hartenstin

• ISBN13: 9783540678991
• ISBN10: 3540678999
• Format: Paperback
• Copyright: 2000-12-01
• Publisher: Springer-Verlag New York Inc

Summary

This book constitues the refereed proceedings of the 10th International Conference on Field-Programmable Logic and Applications, FPL 2000, held in Villach, Austria in August 2000. The 64 revised full papers presented together with eight invited contributions and 21 short papers were carefully reviewed and selected from a total of 131 submissions. The book offers topical sections on network processors, prototyping, dynamic reconfigurability, technology mapping/routing and placement, biologically inspired methods, mobile communciation, design space exploration, optimization, architectures, methodology and technology, compilation, applications, and miscellaneous.

Table of Contents

Invited Keynote
The Rising Wave of Field Programmability	1	(6)
Makimoto, T.
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS	7	(12)
Govindarajan, S.
Vemuri, R.
Network Processors
A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization	19	(10)
Ditmar, J.
Torkelsson, K.
Jantsch, A.
A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors	29	(10)
Tang, X.
Aalsma, M.
Jou, R.
Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits	39	(9)
Iliopoulos, M.
Antonakopoulos, T.
Internet Connected FPL	48	(10)
Fallside, H.
Smith, M.J.S.
Prototyping
Field Programmable Communication Emulation and Optimization for Embedded System Design	58	(10)
Renner, F.-M.
Becker, J.
Glesner, M.
FPGA-Based Emulation: Industrial and Custom Prototyping Solutions	68	(10)
Krupnova, H.
Saucier, G.
FPGA-Based Prototyping for Product Definition	78	(9)
Kress, R.
Pyttel, A.
Sedlmeier, A.
Implementation of Virtual Circuits by Means of the FIPSOC Devices	87	(9)
Canto, E.
Moreno, J.M.
Cabestany, J.
Lacadena, I.
Insenser, J.M.
Dynamically Reconfigurable I
Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT	96	(10)
Gause, J.
Cheung, P.Y.K.
Luk, W.
A Self-Reconfigurable Gate Array Architecture	106	(15)
Sidhu, R.
Wadhwa, S.
Mei, A.
Prasanna, V.K.
Multitasking on FPGA Coprocessors	121	(10)
Simmler, H.
Levinson, L.
Manner, R.
Design Visualisation for Dynamically Reconfigurable Systems	131	(10)
Vasilko, M.
Verification of Dynamically Reconfigurable Logic	141	(10)
Robinson, D.
Lysaght, P.
Miscellaneous I
Design of a Fault Tolerant FPGA	151	(6)
Bartzick, T.
Henze, M.
Kickler, J.
Woska, K.
Real-Time Face Detection on a Configurable Hardware System	157	(6)
McCready, R.
Multifunctional Programmable Single-Board CAN Monitoring Module	163	(6)
Pfeifer, P.
Self-Testing of Linear Segments in User-Programmed FPGAs	169	(6)
Tomaszewicz, P.
Implementing a Fieldbus Interface Using an FPGA	175	(6)
Lias, G.
Valdes, M.D.
Dominguez, M.A.
Moure, M.J.
Technology Mapping and Routing & Placement
Area-Optimized Technology Mapping for Hybrid FPGAs	181	(10)
Krishnamoorthy, S.
Swaminathan, S.
Tessier, R.
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs	191	(10)
Abke, J.
Barke, E.
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards	201	(10)
Chandra Jain, S.
Kumar, A.
Kumar, S.
A Placement Algorithm for FPGA Designs with Multiple I/O Standards	211	(10)
Anderson, J.
Saunders, J.
Nag, S.
Madabhushi, C.
Jayaraman, R.
A Mapping Methodology for Code Trees onto LUT-Based FPGAs	221	(9)
Kropp, H.
Reuter, C.
Biologically Inspired Methods
Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications	230	(10)
Torresen, J.
A Co-processor System with a Virtex FPGA for Evolutionary Computation	240	(10)
Yamaguchi, Y.
Miyashita, A.
Maruyama, T.
Hoshino, T.
System Design with Genetic Algorithms	250	(10)
Bauer, C.
Zipf, P.
Wojtkowiak, H.
Implementing Kak Neural Networks on a Reconfigurable Computing Platform	260	(10)
Zhu, J.
Milne, G.
Compact Spiking Neural Network Implementation in FPGA	270	(7)
Maya, S.
Reynoso, R.
Torres, C.
Arias-Estrada, M.
Invited Keynote
Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play?	277	(9)
Rabaey, J.M.
Invited Papers
From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains	286	(14)
McCaskill, J.S.
Wagler, P.
A Specific Test Methodology for Symmetric SRAM-Based FPGAs	300	(12)
Renovell, M.
Mobile Communication
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communication Applications	312	(10)
Becker, J.
Pionteck, T.
Glesner, M.
Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic	322	(10)
Blaickner, A.
Nagy, O.
Grunbacher, H.
Software Radio Reconfigurable Hardware System (SHaRe)	332	(10)
Reves, X.
Gelonch, A.
Casadevall, F.
Garcia, J.L.
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform	342	(10)
Ramirez, J.
Garcia, A.
Fernandez, P.G.
Parilla, L.
Lloris, A.
Dynamically Reconfigurable II
Partial Run-Time Reconfiguration Using JRTR	352	(9)
McMillan, S.
Guccione, S.A.
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems	361	(10)
Zhang, X.-j.
Ng, K.-w.
Luk, W.
A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs	371	(8)
Rissa, T.
Niittylahti, J.
Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer	379	(10)
ElGindy, H.
Middendorf, M.
Schmeck, H.
Schmidt, B.
Design Space Exploration
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures	389	(11)
Hartenstein, R.
Herz, M.
Hoffmann, Th.
Nageldinger, U.
Mapping of DSP Algorithms on Field Programmable Function Arrays	400	(12)
Heysters, P.M.
Smit, J.
Smit, G.J.M.
Havinga, P.J.M.
On Availability of Bit-Narrow Operations in General-Purpose Applications	412	(10)
Stefanovic, D.
Martonosi, M.
A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers	422	(10)
Grover, R.S.
Shang, W.
Li, Q.
A New Floorplanning Method for FPGA Architectural Research	432	(11)
Wolz, F.
Kolla, R.
Miscellaneous II
Efficient Self-Reconfigurable Implementations Using On-chip Memory	443	(6)
Wadhwa, S.
Dandalis, A.
Design and Implementation of an XC6216 FPGA Model in Verilog	449	(7)
Glasmacher, A.
Woska, K.
Reusable DSP Functions in FPGA's	456	(6)
Andrejas, J.
Trost, A.
A Parallel Pipelined SAT Solver for FPGAs	462	(7)
Redekopp, M.
Dandalis, A.
A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller	469	(6)
Touhafi, A.
Applications I
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems	475	(10)
Yamamoto, O.
Shibata, Y.
Kurosawa, H.
Amano, H.
A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System	485	(10)
Bellis, S.J.
Marnane, W.P.
Reconfigurable Computing for Speech Recognition: Preliminary Findings	495	(10)
Melnikoff, S.J.
James-Roxby, P.B.
Quigley, S.F.
Russell, M.J.
Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic	505	(10)
Ploog, H.
Schmalisch, M.
Timmermann, D.
The Fastest Multiplier on FPGAs with Redundant Binary Representation	515	(10)
Miomo, T.
Yasuoka, K.
Kanazawa, M.
Optimization
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs	525	(10)
Enzler, R.
Jeger, T.
Cottet, D.
Troster, G.
Balancing Logic Utilization and Area Efficiency in FPGAs	535	(10)
Tessier, R.
Giza, H.
Performance Penalty for Fault Tolerance in Roving STARs	545	(10)
Emmert, J.M.
Stroud, C.E.
Cheatham, J.
Taylor, A.M.
Kataria, P.
Abramovici, M.
Optimum Functional Decomposition for LUT-Based FPGA Synthesis	555	(10)
Qiao, J.
Ikeda, M.
Asada, K.
Optimization of Run-Time Reconfigurable Embedded Systems	565	(10)
Eisenring, M.
Platzner, M.
Invited Keynote
It's FPL, Jim - But Not as We Know It! Opportunities for the New Commerical Architectures	575	(10)
Kean, T.
Invited Paper
Reconfigurable Systems: New Activities in Asia	585	(10)
Amano, H.
Shibata, Y.
Uno, M.
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox	595	(10)
Mencer, O.
Hubert, H.
Morf, M.
Flynn, M.J.
Architectures
Stream Computations Organized for Reconfigurable Execution (SCORE)	605	(10)
Caspi, E.
Chu, M.
Huang, R.
Yeh, J.
Wawrzynek, J.
DeHon, A.
Memory Access Schemes for Configurable Processors	615	(11)
Lange, H.
Koch, A.
Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory	626	(10)
Doring, A.C.
Lustig, G.
Combining Serialisation and Reconfiguration for FPGA Designs	636	(10)
Derbyshire, A.
Luk, W.
Methodology and Technology
Multiple-Wordlength Resource Binding	646	(10)
Constantinides, G.A.
Cheung, P.Y.K.
Luk, W.
Automatic Temporal Floorplanning with Guaranteed Solution Feasibility	656	(9)
Vasilko, M.
Benyon-Tinker, G.
A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology	665	(10)
Aoyama, K.
Sawada, H.
Nagoya, A.
Nakajima, K.
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs	675	(10)
Krasniewski, A.
Compilation and Related Issues
Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware	685	(10)
Takayama, A.
Shibata, Y.
Iwai, K.
Amano, H.
Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis	695	(12)
Kastrup, B.
Trum, J.
Moreira, O.
Hoogerbrugge, J.
van Meerbergen, J.
Behavioural Language Compilation with Virtual Hardware Management	707	(11)
Diessel, O.
Milne, G.
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs	718	(11)
Sklyarov, V.
Applications II
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem	729	(10)
Ichikawa, S.
Saito, H.
Udorn, L.
Konishi, K.
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware	739	(10)
Edwards, M.
Green, P.
Multiplexer Based Reconfiguration for Virtex Multipliers	749	(10)
Courtney, T.
Turner, R.
Woods, R.
Efficient Building of Word Recognizer in FPGAs for Term-Document Matrices Construction	759	(10)
Bobda, C.
Lehmann, T.
Short Papers
Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling	769	(4)
Siemers, C.
FPGA Implementation of a Prototype WDM On-Line Scheduler	773	(4)
Cheng, W.W.
Wilton, S.J.E.
Hamidzadeh, B.
An FPGA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems	777	(4)
Hildebrandt, J.
Timmermann, D.
Formal Verification of a Reconfigurable Microprocessor	781	(4)
Sawitzki, S.
Schonherr, J.
Spallek, R.G.
Straube, B.
The Role of the Embedded Memories in the Implementation of Artificial Neural Networks	785	(4)
Gadea, R.
Herrero, V.
Sebastia, A.
Mocholi, A.
Programmable System Level Integration Brings System-on-Chip Design to the Desktop	789	(4)
Lafayette, G.L.
On Applying Software Development Best Practice to FPGAs in Safety-Critical Systems	793	(4)
Hilton, A.
Hall, J.
Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration	797	(4)
Blodget, B.
High Speed Computation of Lattice gas Automata with FPGA	801	(4)
Kobori, T.
Maruyama, T.
Hoshino, T.
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture	805	(5)
Shiozawa, T.
Imlig, N.
Nagami, K.
Oguri, K.
Nagoya, A.
Nakada, H.
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers	810	(4)
Matasaru, B.
Jebelean, T.
Toward Uniform Approach to Design of Evolvable Hardware Based Systems	814	(4)
Sekanina, L.
Sllame, A.M.
Educational Programmable Hardware Prototyping and Verification System	818	(4)
Trost, A.
Zemva, A.
Zajc, B.
A Stream Processor Architecture Based on the Configurable CEPRA-S	822	(4)
Hoffmann, R.
Ulmann, B.
Volkmann, K.-P.
Waldschmidt, S.
An Innovative Approach to Couple EDA Tools with Reconfigurable Hardware	826	(4)
Hatnik, U.
Haufe, J.
Schwarz, P.
FPL Curriculum at Tallinn Technical University	830	(4)
Tammemae, K.
Evartson, T.
The Modular Architecture of SYNTHUP, FPGA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing	834	(4)
Raczinski, J.-M.
Sladek, S.
A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor	838	(4)
Brinkmann, A.
Langen, D.
Ruckert, U.
Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers	842	(4)
Noguera, J.
Badia, R.M.
Wireless Base Station Design Using a Reconfigurable Communications Processor	846	(3)
Phillips, C.
Placement of Linear Arrays	849	(4)
Fabiani, E.
Lavenier, D.
Author Index	853