Flash Memories

by Cappelletti, Paulo; Golla, Carla; Olivo, Piero; Zanoni, Enrico

• ISBN13: 9780792384878
• ISBN10: 0792384873
• Format: Hardcover
• Copyright: 1999-05-01
• Publisher: Kluwer Academic Pub

Summary

Most of the current applications of electronics require non-volatile memories, which can keep stored information when the power supply is switched off. Flash memories (in which a single cell can be electrically programmed and a large number of cells are usually electrically erased at the same time) are the most versatile non-volatile memories. They are widely used to store the basic input-output system (BIOS) of personal computers, the software and personal data of cellular phones, identification codes in smart cards and many other applications. Flash memories allow software updates, change of passwords and codes, and reconfiguration of the system in the field. They can be designed and optimized to create large-size memories which can successfully substitute hard disks for specific applications, having lower power consumption and weight, shorter access times, and far better robustness. This book is devoted entirely to flash memories and has been designed to provide comprehensive information on basic memory cell structures, device physics and technology, simulation circuit architecture, system issues, testing and reliability. It also provides data on advanced subjects related to multi-level storage cells, embedded memories and system applications of flash memories.

Table of Contents

Flash Memories: An Overview	1	(36)
P. Olivo
E. Zanoni
Role of Non Volatile Memories in Microelectronic Systems and in Semiconductor Market	1	(2)
Evolution of Non-volatile Memories	3	(1)
The Floating Gate Device	4	(3)
Charge Injection Mechanisms	7	(1)
Erasable Programmable Read Only Memories	7	(2)
The Floating gate Avalanche-injection MOS transistor (FAMOS) Cell	7	(1)
The basic Erasable Programmable Read Only Memory (EPROM)	8	(1)
Electrically Erasable Programmable Read Only Memories	9	(6)
The FLOating gate Thin Oxide (FLOTOX) Memory Cell	9	(1)
Textured Polysilicon Cells	10	(2)
The EEPROM Architecture	12	(1)
Ferroelectric Memories	13	(2)
Flash Memories: The Basic ETOX Cell. Programming and Erasing Mechanisms	15	(1)
Memory NOR Architecture and Related Issues	16	(8)
The NAND Flash Mass Storage Concept	24	(2)
Embedded Flash Memories	26	(1)
The Future of Flash Memories	27	(10)
Evolution of Flash Memory Technology	27	(2)
Non Volatile Memories Market Development	29	(4)
References	33	(4)
The Industry Standard Flash Memory Cell	37	(54)
P. Pavan
R. Bez
Introduction	38	(4)
Basic Structure	42	(4)
Operating Conditions	46	(12)
Read	46	(1)
Program	47	(6)
Erase	53	(5)
Technology and Process	58	(16)
Isolation	60	(1)
Well and Channel Doping	61	(3)
Cell Structure Definition	64	(4)
Interlevel Dielectrics	68	(2)
Interconnections	70	(4)
Final Passivation	74	(1)
Yield and Reliability	74	(7)
Retention	75	(1)
Endurance	75	(1)
Reading Disturbs	76	(1)
Programming Disturbs	77	(2)
Erasing Disturbs	79	(2)
Scaling Issues	81	(10)
References	83	(8)
Binary and Multilevel Flash Cells	91	(62)
B. Eitan
A. Roy
Introduction to Flash Cell Design	91	(2)
Binary Flash Cells	93	(44)
Figures of Merit	93	(1)
Cell Design Complication Hierarchy from ROM to Flash	94	(2)
Basis for Flash Cells/Array Classification	96	(2)
Detailed Description of Flash Cells and Architectures	98	(33)
Scaling and Conclusions	131	(6)
Multilevel Flash Cells	137	(16)
Introduction to the Concept of Multilevel Flash	137	(1)
Multilevel Programming Mechanisms	138	(4)
Architectures for Multilevel Flash Memories	142	(4)
Scaling and Trade-Offs for Multilevel	146	(1)
References	147	(6)
Physical Aspects of Cell Operation and Reliability	153	(88)
L. Selmi
C. Fiegna
Introduction	153	(2)
Electronic Properties of Carriers and MOS Structures	155	(6)
Electrons in Crystals	155	(1)
Electrons as Classical Particles	156	(1)
Silicon	157	(1)
Silicon Dioxide	157	(2)
Silicon-Silicon Dioxide Interface	159	(1)
Oxide and Interface Traps	159	(2)
Fundamentals of Tunneling Phenomena	161	(4)
Basic Concepts and the WKB Approximation	161	(1)
Transmission Coefficient	162	(3)
Tunneling Current	165	(1)
Tunneling Phenomena in MOSFETs	165	(11)
Fowler-Nordheim and Direct Tunneling Through Gate Oxides	166	(1)
Modeling the Tunnel Current of MOS Structures	167	(3)
Band-to-band and Trap-to-band Tunneling	170	(4)
Modeling the Band-to-band and Trap-to-band Tunneling Current	174	(2)
Fundamentals of Carrier Transport	176	(9)
The Distribution Function	176	(2)
The Boltzmann Transport Equation	178	(2)
Scattering	180	(1)
The Carrier Distribution in Thermal Equilibrium	181	(1)
Carrier Distributions in Homogeneous Electric Fields	182	(2)
The Effective Temperature Model	184	(1)
Hot Carrier Effects in MOSFETs	185	(22)
Carrier Heating in MOSFETs and Flash Cells	186	(3)
MOSFET Design and Carrier Heating	189	(1)
Simplified Models of Carrier Heating	190	(1)
Average Energy	190	(1)
Carrier Distribution	191	(1)
Impact Ionization	192	(2)
Substrate Current	194	(3)
Hot Carrier Injection into SiO+2	197	(1)
Distribution Function	198	(1)
Injection Probability	198	(1)
Gate Current	199	(1)
Channel Hot Electron Injection	199	(2)
Drain Avalanche Hot Carrier Injection	201	(1)
Secondary Generated Hot Electron Injection	202	(1)
Substrate Hot Electron Injection	203	(2)
Implications for Device Operation	205	(1)
Hot Carrier Effects at Low Voltages	206	(1)
Oxide Degradation due to High Field Stress	207	(10)
Oxide Wear-out and SILC	207	(3)
Stress Induced Leakage Currents (SILC)	210	(1)
Oxide Breakdown	211	(2)
Lifetime Evaluation Models	213	(1)
SILC Lifetime Evaluation Model	214	(1)
Breakdown Lifetime Evaluation Model	215	(2)
Oxide and Interface Degradation due to Hot Carrier Injection	217	(24)
Homogeneous Hot Carrier Degradation	217	(1)
n-channel Devices	217	(1)
p-channel Devices	218	(1)
Non-homogeneous Hot Carrier Degradation	218	(3)
Lifetime Evaluation Models	221	(2)
References	223	(18)
Memory Architecture and Related Issues	241	(120)
M. Branchetti
G. Campardo
S. Commodaro
S. Ghezzi
A. Ghilardelli
C. Golla
M. Maccarrone
I. Martines
R. Micheloni
J. Mulatti
M. Zammattio
S. Zanardi
Flash Architecture: General Overview	241	(16)
Flash Architecture Scenario	242	(1)
NOR Cell Operation and Array Organization	243	(7)
Flash Memory User Interface	250	(3)
Flash Memory Operations: Overview	253	(1)
Read Path Building Blocks Description	253	(3)
Program Path Building Blocks Description	256	(1)
Erase Path Building Blocks Description	256	(1)
Read Path: Decoding	257	(13)
Predecoding	259	(1)
Row Decoder	259	(4)
Column Decoder	263	(1)
Hierarchical Decoder	264	(2)
Low VCC Problems	266	(1)
Boost Concept: Continuous Boost and ``One-shot'' Bost	267	(1)
A New Boost Approach: Miniboost	268	(2)
Read Path: Input and Output Buffers	270	(10)
Input Buffer	270	(2)
Output Buffer	272	(3)
Noise Issues	275	(2)
High Voltage Tolerance	277	(3)
Read Path: Sensing Techniques	280	(34)
Sensing Techniques: An Overview	281	(4)
Differential Sensing Technique	285	(4)
Differential Sensing Technique with Offset Current	289	(4)
Differential Semi-Parallel Sensing Technique	293	(2)
Reading Speed-up Techniques	295	(9)
From EPROM to Flash	304	(1)
Reading Flash Memories with Depleted Bits	305	(3)
Low Voltage Flash Read	308	(4)
Reference Problems	312	(2)
Program Operation Circuitry	314	(13)
Cell Programming Voltages: Optimum Choice	314	(1)
Typical Program Path	315	(2)
Drain Voltage Regulation: Principles and Basic Circuits	317	(3)
Gate Voltage Regulation Fundamentals	320	(7)
Erase Operation Circuitry	327	(10)
Double Supply Voltage Approach	329	(1)
Source Erase Circuitry	329	(1)
Slow Discharge of Critical Nodes	330	(1)
Single Supply Voltage Approach	331	(1)
Charge Pumping	332	(3)
Voltage Regulators	335	(1)
Source Switch	336	(1)
Control Logic and Embedded Algorithms	337	(13)
Logic Architecture	339	(4)
Embedded Algorithms	343	(1)
Sequencer (Pseudo-Microcontroller)	344	(1)
Finite State Machine	344	(1)
Program Flow	344	(2)
Erase Flow	346	(2)
Erase Suspend-Erase Resume	348	(1)
Testability Issues	348	(2)
Redundancy and Error Correction Codes	350	(11)
The Yield	350	(2)
Static Redundancy	352	(1)
Wafer Yield	353	(1)
A Real Case	354	(2)
Error Correction Codes	356	(5)
Multilevel Flash Memories	361	(38)
G. Torelli
M. Lanzoni
A. Manstretta
B. Ricco
Introduction	362	(6)
The Multilevel Approach	362	(2)
Basic Issues for ML Storage	364	(4)
Array Architectures for Multilevel Flash Memories	368	(5)
NOR Architecture with CHE Programming	369	(2)
NOR Architecture with FN Programming	371	(1)
NAND Architecture	371	(2)
Multilevel Sensing	373	(9)
Signal Production and Recognition	374	(2)
Sensing Schemes	376	(6)
Multilevel Programming	382	(7)
Program-and-Verify Approaches	384	(3)
Self-Controlled Approaches	387	(2)
Conclusions	389	(10)
References	391	(8)
Flash Memory Reliability	399	(44)
P. Cappelletti
A. Modelli
Introduction	399	(2)
Memory Array V+t Distributions and Tunnel Oxide ``Defects''	401	(8)
Main Yield and Reliability Issues	409	(8)
Over-Erasing	409	(2)
Program Disturbs	411	(3)
Read Disturb	414	(1)
Program/Erase Endurance	415	(1)
Data Retention	416	(1)
Testing for Reliability	417	(1)
Failure Modes Induced by Program/Erase Cycling	418	(18)
Memory Cell Intrinsic Endurance	418	(4)
The Behavior of Tail Bits	422	(1)
Single Bit Failure Mechanisms	422	(1)
The Erratic Erase Phenomenon	423	(3)
Single Bit Data Loss after Program/Erase Cycling	426	(4)
Gain Degradation	430	(6)
Multilevel Storage Reliability	436	(3)
Conclusion	439	(4)
References	439	(4)
Flash Memory Testing	443	(38)
G. Casagrande
Introduction	443	(3)
Impact of Testing on Product Cost	443	(1)
Impact on Product Life Cycle	444	(1)
Objectives of Production Testing	445	(1)
Testing Versus Quality and Reliability	445	(1)
Flash Testing Aspects	446	(4)
Flash Functional Model	446	(1)
Oxide Stress in a Flash	446	(1)
Flash Testing Aspects	447	(1)
Conceptual Test Flow	448	(2)
Flash Testability Tools	450	(10)
Focus on Cell and Technology	450	(1)
Direct Memory Access	451	(1)
Vt Measurement	452	(2)
Stress Modes	454	(1)
Depletion/Low-Vt Test	455	(2)
Focus on Test Productivity	457	(1)
Focus on Design	457	(1)
Flash Design Testability: an Example	458	(2)
Fault Repairing	460	(6)
Error Correction	462	(1)
Redundancy	462	(2)
Diagnosis and Repairing	464	(1)
Testability Tools for Redundancy	465	(1)
Production Testing	466	(4)
DC Tests	467	(1)
Functional Testing	468	(1)
AC Read/Command Interface	469	(1)
Erase/Program Performance; Endurance	470	(1)
Reliability	470	(1)
Test Productivity	470	(4)
Impact on Tester Structure	471	(2)
Parallel Testing Final Test	473	(1)
Parallel Testing at EWS	473	(1)
Product Characterization	474	(4)
Conclusions	478	(3)
References	479	(2)
Flash Memories: Market, Marketing and Economic Challenges	481
B. Beverina
P. Berge
C. Kunkel
G. Moy
A. Damiano
R. Ferrara
A. Re
Introduction	482	(1)
Market Segmentations	483	(12)
Application Segments and Subsegments	485	(3)
Technology, Performances and Applications	488	(4)
Segment Dynamics	492	(1)
Commodity or Non-Commodity?	493	(2)
Customer/Supplier Relationship	495	(1)
The Development of the Flash Market	496	(3)
Flash Memory and the ``Economy''	499	(1)
Applications More in Detail	500	(25)
Survey	500	(3)
Flash in Mobile Phones and Terminals	503	(5)
Flash in the BIOS	508	(7)
Flash in Automotive	515	(10)
Conclusions	525
References	526