From ASICs to SOCs A Practical Approach

by Nekoogar, Farzad; Nekoogar, Faranak

• ISBN13: 9780130338570
• ISBN10: 0130338575
• Edition: 1st
• Format: Paperback
• Copyright: 2003-05-28
• Publisher: Pearson

Summary

From ASICs to SOCs: A Practical Approach, by Farzad Nekoogar and Faranak Nekoogar, covers the techniques, principles, and everyday realities of designing ASICs and SOCs. Material includes current issues in the field, front-end and back-end designs, integration of IPs on SOC designs, and low-power design techniques and methodologies. Appropriate for practicing chip designers as well as graduate students in electrical engineering.

Author Biography

Farzad Nekoogar has over 15 years of experience in design and verification of ASICs (front-end and back-end), SOCs, FPGAs, boards, and systems. He has lectured at the University of California on signal processing, chip design, and theoretical physics. Faranak Nekoogar has many years of experience verifying ASICs and SOCs. She is currently researching the development of low-power algorithms for Ultra-Wideband (UWB) communications in the Department of Applied Science at the University of California-Davis

Table of Contents

List of Abbreviations	xiii
Preface	xvii
Acknowledgments	xxi
Introduction	1	(20)
Introduction	1	(1)
Voice Over IP SOC	2	(5)
Intellectual Property	7	(5)
SOC Design Challenges	12	(4)
Design Methodology	16	(2)
Summary	18	(2)
References	20	(1)
Overview of ASICs	21	(22)
Introduction	21	(4)
Methodology and Design Flow	25	(7)
FPGA to ASIC Conversion	32	(2)
Verification	34	(6)
Summary	40	(1)
References	41	(2)
SOC Design and Verification	43	(38)
Introduction	43	(1)
Design for Integration	44	(3)
SOC Verification	47	(9)
Set-Top-Box SOC	56	(1)
Set-Top-Box SOC Example	57	(22)
Summary	79	(1)
References	79	(2)
Physical Design	81	(30)
Introduction	81	(1)
Overview of Physical Design Flow	82	(5)
Some Tips and Guidelines for Physical Design	87	(6)
Modern Physical Design Techniques	93	(15)
Summary	108	(1)
References	109	(2)
Low-Power Design	111	(40)
Introduction	111	(1)
Power Dissipation	112	(5)
Low-Power Design Techniques and Methodologies	117	(23)
Low-Power Design Tools	140	(5)
Tips and Guidelines for Low-Power Design	145	(1)
Summary	146	(1)
References	147	(4)
A Low-Power Design Tools	151	(8)
PowerTheater	151	(2)
PowerTheater Analyst	153	(2)
PowerTheater Designer	155	(4)
B Open Core Protocol (OCP)	159	(6)
Highlights	160	(1)
Capabilities	160	(1)
Advantages	161	(1)
Key Features	162	(3)
C Phase-Locked Loops (PLLs)	165	(8)
PLL Basics	165	(1)
PLL Ideal Behavior	166	(2)
PLL Errors	168	(5)
Glossary	173	(10)
Index	183

Excerpts

PrefaceThe term SOC (system-on-a-chip) has been used in the electronic industry over the last few years. However, there are still a lot of misconceptions associated with this term. A good number of practicing engineers don't really understand the differences between ASICs and SOCs. The fact that the same EDA tools are used for both ASICs and SOCs design and verification doesn't help to reduce the misconceptions.This book describes the practical aspects of ASIC and SOC design and verification. It reflects the current issues facing ASIC/ SOC designers.The following items characterize the book: It deals with everyday issues that ASIC/SOC designers have to face as opposed to generic textbook examples covered in other books. It emphasizes principles and techniques as opposed to specific tools. Once the designers understand the underlying principles of practical design, they can apply them with various tools. FPGAs will not be covered in this book. However, in Chapter 2 we cover a short section on FPGA to ASIC conversion. Earlier books have covered design and verification of FPGAs adequately. It provides tips and guidelines for front-end and back-end designs. Modern physical design techniques are covered. Low-power design techniques and methodologies are explored for both ASICs and SOCs.This book is to be used for self-study by practicing engineers. Design and verification engineers who are working with ASICs and SOCs will find the book very useful. Upper-level undergraduate and graduate students in electrical engineering can use it as a reference book in courses in logic and chip design and related topics. The material covered in the book requires understanding of EDA tools as well as front-end and back-end processes in chip design. An initial course in logic design is required. The book is organized in the following fashion.In Chapter 1 we introduce the goals of this manuscript. The differences between ASICs and SOCs are introduced. The concept of Intellectual Property (IP) is covered as well as an overview of design methodologies.SOC design challenges such as integration of IPs are also covered. A gateway VOIP (Voice Over IP) SOC example is given in this chapter.Chapter 2 covers an overview of ASIC design concepts, methodology, and front-end design flow. Useful guidelines for hierarchical design methodology are presented such as placement-based synthesis and interface logic models. Some key questions that ASIC designers should consider when designing ASICs are presented. FPGA to ASIC conversion is covered in Section 2.3. An overview of verification and Design for Test (DFT) techniques are also presented in this chapter.Chapter 3 continues with the VOIP SOC example from Chapter 1. Design for integration is covered in Section 3.2. Section 3.3 covers SOC verification planning guidelines such as resource planning and regression planning. Automation and IP verification are also covered in Section 3.3. This chapter ends with a detailed design example of a Set-Top Box (STB).Chapter 4 covers an overview of the physical design flow. Some tips and guidelines for physical design are given such as logical vs. physical hierarchy, multiple placements and routing, and nonroutable congested areas.Two examples of modern physical-design techniques are presented in Section 4.4. These methods each overcome the problems associated with traditional physical design techniques.In Chapter 5 we present low-power design techniques. In this chapter, sources of power dissipation in CMOS devices are discussed. Several methods of power optimization at various levels of abstraction for ASICS and SOCs are explained. These techniques include: algorithm-level optimization, architecture-level optimization, RT-level optimization, and gate-level optimization. Appendix A should be used in conjunction with this chapter.