Preface to the first edition | p. xi |
Preface to the second edition | p. xiii |
Physical constants and unit conversions | p. xv |
List of symbols | p. xvi |
Introduction | p. 1 |
Evolution of VLSI Device Technology | p. 1 |
Historical Perspective | p. 1 |
Recent Developments | p. 4 |
Modern VLSI Devices | p. 4 |
Modern CMOS Transistors | p. 4 |
Modern Bipolar Transistors | p. 5 |
Scope and Brief Description of the Book | p. 6 |
Basic Device Physics | p. 11 |
Electrons and Holes in Silicon | p. 11 |
Energy Bands in Silicon | p. 11 |
n-Type and p-Type Silicon | p. 17 |
Carrier Transport in Silicon | p. 23 |
Basic Equations for Device Operation | p. 27 |
p-n Junctions | p. 35 |
Energy-Band Diagrams for a p-n Diode | p. 35 |
Abrupt Junctions | p. 38 |
The Diode Equation | p. 46 |
Current-Voltage Characteristics | p. 51 |
Time-Dependent and Switching Characteristics | p. 64 |
Diffusion Capacitance | p. 70 |
MOS Capacitors | p. 72 |
Surface Potential: Accumulation, Depletion, and Inversion | p. 72 |
Electrostatic Potential and Charge Distribution in Silicon | p. 78 |
Capacitances in an MOS Structure | p. 85 |
Polysilicon-Gate Work Function and Depletion Effects | p. 91 |
MOS under Nonequilibrium and Gated Diodes | p. 94 |
Charge in Silicon Dioxide and at the Silicon-Oxide Interface | p. 98 |
Effect of Interface Traps and Oxide Charge on Device Characteristics | p. 103 |
Metal-Silicon Contacts | p. 108 |
Static Characteristics of a Schottky Barrier Diode | p. 108 |
Current Transport in a Schottky Barrier Diode | p. 115 |
Current-Voltage Characteristics of a Schottky Barrier Diode | p. 115 |
Ohmic Contacts | p. 120 |
High-Field Effects | p. 122 |
Impact Ionization and Avalanche Breakdown | p. 122 |
Band-to-Band Tunneling | p. 125 |
Tunneling into and through Silicon Dioxide | p. 127 |
Injection of Hot Carriers from Silicon into Silicon Dioxide | p. 133 |
High-Field Effects in Gated Diodes | p. 135 |
Dielectric Breakdown | p. 137 |
Exercises | p. 141 |
Mosfet Devices | p. 148 |
Long-Channel Mosfets | p. 148 |
Drain-Current Model | p. 149 |
Mosfet I-V Characteristics | p. 155 |
Subthreshold Characteristics | p. 163 |
Substrate Bias and Temperature Dependence of Threshold Voltage | p. 166 |
Mosfet Channel Mobility | p. 169 |
Mosfet Capacitances and Inversion-Layer Capacitance Effect | p. 172 |
Short-Channel Mosfets | p. 175 |
Short-Channel Effect | p. 176 |
Velocity Saturation and High-Field Transport | p. 186 |
Channel Length Modulation | p. 195 |
Source-Drain Series Resistance | p. 196 |
Mosfet Degradation and Breakdown at High Fields | p. 196 |
Exercises | p. 201 |
CMOS Device Design | p. 204 |
Mosfet Scaling | p. 204 |
Constant-Field Scaling | p. 204 |
Generalized Scaling | p. 207 |
Nonscaling Effects | p. 210 |
Threshold Voltage | p. 212 |
Threshold-Voltage Requirement | p. 213 |
Channel Profile Design | p. 217 |
Nonuniform Doping | p. 224 |
Quantum Effect on Threshold Voltage | p. 234 |
Discrete Dopant Effects on Threshold Voltage | p. 239 |
Mosfet Channel Length | p. 242 |
Various Definitions of Channel Length | p. 242 |
Extraction of the Effective Channel Length | p. 244 |
Physical Meaning of Effective Channel Length | p. 248 |
Extraction of Channel Length by C-V Measurements | p. 252 |
Exercises | p. 254 |
CMOS Performance Factors | p. 256 |
Basic CMOS Circuit Elements | p. 256 |
CMOS Inverters | p. 256 |
CMOS NAND and NOR Gates | p. 266 |
Inverter and NAND Layouts | p. 270 |
Parasitic Elements | p. 273 |
Source-Drain Resistance | p. 274 |
Parasitic Capacitances | p. 277 |
Gate Resistance | p. 280 |
Interconnect R and C | p. 283 |
Sensitivity of CMOS Delay to Device Parameters | p. 289 |
Propagation Delay and Delay Equation | p. 289 |
Delay Sensitivity to Channel Width, Length, and Gate Oxide Thickness | p. 296 |
Sensitivity of Delay to Power-supply Voltage and Threshold Voltage | p. 299 |
Sensitivity of Delay to Parasitic Resistance and Capacitance | p. 301 |
Delay of Two-Way NAND and Body Effect | p. 304 |
Performance Factors of Advanced CMOS Devices | p. 307 |
Mosfets in RF Circuits | p. 308 |
Effect of Transport Parameters on CMOS Performance | p. 311 |
Low-Temperature CMOS | p. 312 |
Exercises | p. 315 |
Bipolar Devices | p. 318 |
n-p-n Transistors | p. 318 |
Basic Operation of a Bipolar Transistor | p. 322 |
Modifying the Simple Diode Theory for Describing Bipolar Transistors | p. 322 |
Ideal Current-Voltage Characteristics | p. 327 |
Collector Current | p. 329 |
Base Current | p. 330 |
Current Gains | p. 334 |
Ideal Ic-VCE Characteristics | p. 336 |
Characteristics of a Typical n-p-n Transistor | p. 337 |
Effect of Emitter and Base Series Resistances | p. 338 |
Effect of Base-Collector Voltage on Collector Current | p. 340 |
Collector Current Falloff at High Currents | p. 343 |
Nonideal Base Current at Low Currents | p. 347 |
Bipolar Device Models for Circuit and Time-Dependent Analyses | p. 352 |
Basic de Model | p. 352 |
Basic ac Model | p. 355 |
Small-Signal Equivalent-Circuit Model | p. 356 |
Emitter Diffusion Capacitance | p. 359 |
Charge-Control Analysis | p. 361 |
Breakdown Voltages | p. 366 |
Common-Base Current Gain in the Presence of Base-Collector Junction Avalanche | p. 367 |
Saturation Currents in a Transistor | p. 369 |
Relation Between BV CEO and BV CBO | p. 370 |
Exercises | p. 371 |
Bipolar Device Design | p. 374 |
Design of the Emitter Region | p. 374 |
Diffused or Implanted-and-Diffused Emitter | p. 375 |
Polysilicon Emitter | p. 376 |
Design of the Base Region | p. 377 |
Relationship between Base Sheet Resistivity and Collector Current Density | p. 378 |
Intrinsic-Base Dopant Distribution | p. 380 |
Electric Field in the Quasineutral Intrinsic Base | p. 381 |
Base Transit Time | p. 384 |
Design of the Collector Region | p. 385 |
Collector Design When There is Negligible Base Widening | p. 387 |
Collector Design When There is Appreciable Base Widening | p. 388 |
SiGe-Base Bipolar Transistors | p. 389 |
Transistors Having a Simple Linearly Graded Base Bandgap | p. 390 |
Base Current When Ge Is Present in the Emitter | p. 396 |
Transistors Having a Trapezoidal Ge Distribution in the Base | p. 401 |
Transistors Having a Constant Ge Distribution in the Base | p. 406 |
Effect of Emitter Depth Variation on Device Characteristics | p. 410 |
Some Optimal Ge Profiles | p. 414 |
Base-Width Modulation by VBE | p. 419 |
Reverse-Mode I-V Characteristics | p. 423 |
Heterojunction Nature of a SiGe-Base Bipolar Transistor | p. 426 |
Modern Bipolar Transistor Structures | p. 429 |
Deep-Trench Isolation | p. 429 |
Polysilicon Emitter | p. 430 |
Self-Aligned Polysilicon Base Contact | p. 430 |
Pedestal Collector | p. 431 |
SiGe-Base | p. 431 |
Exercises | p. 432 |
Bipolar Performance Factors | p. 437 |
Figures of Merit of a Bipolar Transistor | p. 437 |
Cutoff Frequency | p. 437 |
Maximum Oscillation Frequency | p. 440 |
Ring Oscillator and Gate Delay | p. 440 |
Digital Bipolar Circuits | p. 441 |
Delay Components of a Logic Gate | p. 442 |
Device Structure and Layout for Digital Circuits | p. 445 |
Bipolar Device Optimization for Digital Circuits | p. 447 |
Design Points for a Digital Circuit | p. 447 |
Device Optimization When there is Significant Base Widening | p. 448 |
Device Optimization When There is Negligible Base Widening | p. 449 |
Device Optimization for Small Power-Delay Product | p. 453 |
Bipolar Device Optimization from Some Data Analyses | p. 455 |
Bipolar Device Scaling for ECL Circuits | p. 457 |
Device Scaling Rules | p. 458 |
Limits in Bipolar Device Scaling for ECL Circuits | p. 460 |
Bipolar Device Optimization and Scaling for RF and Analog Circuits | p. 463 |
The Single-Transistor Amplifier | p. 463 |
Optimizing the Individual Parameters | p. 464 |
Technology for RF and Analog Bipolar Devices | p. 467 |
Limits in Scaling Bipolar Transistors for RF and Analog Applications | p. 468 |
Comparing a SiGe-Base Bipolar Transistor with a GaAs HBT | p. 469 |
Exercises | p. 472 |
Memory Devices | p. 476 |
Static Random-Access Memory | p. 477 |
CMOS SRAM Cell | p. 478 |
Other Bistable MOSFET SRAM Cells | p. 486 |
Bipolar SRAM Cell | p. 487 |
Dynamic Random-Access Memory | p. 495 |
Basic DRAM Cell and Its Operation | p. 496 |
Device Design and Scaling Considerations for a DRAM Cell | p. 499 |
Nonvolatile Memory | p. 500 |
Mosfet Nonvolatile Memory Devices | p. 501 |
Flash Memory Arrays | p. 507 |
Floating-Gate Nonvolatile Memory Cells | p. 511 |
Nonvolatile Memory Cells with Charge Stored in Insulator | p. 514 |
Exercise | p. 516 |
Silicon-on-Insulator Devices | p. 517 |
SOI CMOS | p. 517 |
Partially Depleted SOI Mosfets | p. 518 |
Fully Depleted SOI Mosfets | p. 520 |
Thin-Silicon SOI Bipolar | p. 523 |
Fully Depleted Collector Mode | p. 524 |
Partially Depleted Collector Mode | p. 526 |
Accumulation Collector Mode | p. 527 |
Discussion | p. 527 |
Double-Gate Mosfets | p. 529 |
An Analytic Drain Current Model for Symmetric DG Mosfets | p. 529 |
The Scale Length of Double-Gate Mosfets | p. 533 |
Fabrication Requirements and Challenges of DG Mosfets | p. 534 |
Multiple-Gate Mosfets | p. 536 |
Exercise | p. 537 |
CMOS Process Flow | p. 538 |
Outline of a Process for Fabricating Modern n-p-n Bipolar Transistors | p. 542 |
Einstein Relations | p. 543 |
Spatial Variation of Quasi-Fermi Potentials | p. 546 |
Generation and Recombination Processes and Space-Charge-Region Current | p. 553 |
Diffusion Capacitance of a p-n Diode | p. 562 |
Image-Force-Induced Barrier Lowering | p. 569 |
Electron-Initiated and Hole-Initiated Avalanche Breakdown | p. 573 |
An Analytical Solution for the Short-Channel Effect in Subthreshold | p. 575 |
Generalized Mosfet Scale Length Model | p. 582 |
Drain Current Model of a Ballistic Mosfet | p. 588 |
Quantum-Mechanical Solution in Weak Inversion | p. 594 |
Power Gain of a Two-Port Network | p. 598 |
Unity-Gain Frequencies of a Mosfet Transistor | p. 601 |
Determination of Emitter and Base Series Resistances | p. 605 |
Intrinsic-Base Resistance | p. 610 |
Energy-Band Diagram of a Si-SiGe n-p Diode | p. 614 |
ftand fmax of a Bipolar Transistor | p. 617 |
References | p. 623 |
Index | p. 644 |
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