Hardware Verification Track | |
Model Checking PSL Using HOL and SMV | p. 1 |
Using Linear Programming Techniques for Scheduling-Based Random Test-Case Generation | p. 16 |
Extracting a Simplified View of Design Functionality Based on Vector Simulation | p. 34 |
Automatic Fault Localization for Property Checking | p. 50 |
Verification of Data Paths Using Unbounded Integers: Automata Strike Back | p. 65 |
Tools Track | |
Smart-Lint: Improving the Verification Flow | p. 81 |
Model-Driven Development with the jABC | p. 92 |
Detecting Design Flaws in UML State Charts for Embedded Software | p. 109 |
A Panel: Unpaved Road Between Hardware Verification and Software Testing Techniques | p. 122 |
An Open Source Simulation Model of Software Development and Testing | p. 124 |
Software Testing Track | |
ExpliSAT: Guiding SAT-Based Software Verification with Explicit States | p. 138 |
Evolutionary Testing: A Case Study | p. 155 |
A Race-Detection and Flipping Algorithm for Automated Testing of Multi-threaded Programs | p. 166 |
Explaining Intermittent Concurrent Bugs by Minimizing Scheduling Noise | p. 183 |
Testing the Machine in the World | p. 198 |
Choosing a Test Modeling Language: A Survey | p. 204 |
Making Model-Based Testing More Agile: A Use Case Driven Approach | p. 219 |
Author Index | p. 235 |
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