Abstract of keynote : insight, not (random) numbers : an embedded perspective | p. 3 |
Compiler-assisted memory encryption for embedded processors | p. 7 |
Leveraging high performance data cache techniques to save power in embedded systems | p. 23 |
Applying decay to reduce dynamic power in set-associative caches | p. 38 |
Virtual registers : reducing register pressure without enlarging the register file | p. 57 |
Bounds checking with taint-based analysis | p. 71 |
Reducing exit stub memory consumption in code caches | p. 87 |
Reducing branch misprediction penalties via adaptive pipeline scaling | p. 105 |
Fetch gating control through speculative instruction window weighting | p. 120 |
Dynamic capacity-speed tradeoffs in SMT processor caches | p. 136 |
Branch history matching : branch predictor warmup for sampled simulation | p. 153 |
Sunflower : full-system, embedded microarchitecture evaluation | p. 168 |
Efficient program power behavior characterization | p. 183 |
Performance/energy optimization of DSP transforms on the XScale processor | p. 201 |
Arx : a toolset for the efficient simulation and direct synthesis of high-performance signal processing algorithms | p. 215 |
A throughput-driven task creation and mapping for network processors | p. 227 |
MiDataSets : creating the conditions for a more realistic evaluation of iterative optimization | p. 245 |
Evaluation of offset assignment heuristics | p. 261 |
Customizing the datapath and ISA of soft VLIW processors | p. 276 |
Instruction set extension generation with considering physical constraints | p. 291 |
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