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9783540693376

High Performance Embedded Architectures and Compilers: Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings

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  • ISBN13:

    9783540693376

  • ISBN10:

    3540693378

  • Format: Paperback
  • Copyright: 2007-03-06
  • Publisher: Springer Verlag

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Supplemental Materials

What is included with this book?

Summary

This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in Januar 2007. The 19 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on secure and low-power embedded memory systems, architecture/compiler optimizations for efficient embedded processing, adaptive microarchitectures, architecture evaluation techniques, generation of efficient embedded applications, as well as optimizations and architectural tradeoffs for embedded systems.

Table of Contents

Abstract of keynote : insight, not (random) numbers : an embedded perspectivep. 3
Compiler-assisted memory encryption for embedded processorsp. 7
Leveraging high performance data cache techniques to save power in embedded systemsp. 23
Applying decay to reduce dynamic power in set-associative cachesp. 38
Virtual registers : reducing register pressure without enlarging the register filep. 57
Bounds checking with taint-based analysisp. 71
Reducing exit stub memory consumption in code cachesp. 87
Reducing branch misprediction penalties via adaptive pipeline scalingp. 105
Fetch gating control through speculative instruction window weightingp. 120
Dynamic capacity-speed tradeoffs in SMT processor cachesp. 136
Branch history matching : branch predictor warmup for sampled simulationp. 153
Sunflower : full-system, embedded microarchitecture evaluationp. 168
Efficient program power behavior characterizationp. 183
Performance/energy optimization of DSP transforms on the XScale processorp. 201
Arx : a toolset for the efficient simulation and direct synthesis of high-performance signal processing algorithmsp. 215
A throughput-driven task creation and mapping for network processorsp. 227
MiDataSets : creating the conditions for a more realistic evaluation of iterative optimizationp. 245
Evaluation of offset assignment heuristicsp. 261
Customizing the datapath and ISA of soft VLIW processorsp. 276
Instruction set extension generation with considering physical constraintsp. 291
Table of Contents provided by Blackwell. All Rights Reserved.

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