High Performance Switches and Routers

by Chao, H. Jonathan; Liu, Bin

• ISBN13: 9780470053676
• ISBN10: 0470053674
• Edition: 1st
• Format: Hardcover
• Copyright: 2007-04-06
• Publisher: Wiley-IEEE Press

Summary

As Internet traffic grows and demands for quality of service become stringent, researchers and engineers can turn to this go-to guide for tested and proven solutions. This text presents the latest developments in high performance switches and routers, coupled with step-by-step design guidance and more than 550 figures and examples to enable readers to grasp all the theories and algorithms used for design and implementation.

Author Biography

H. Jonathan Chao, PhD, is Department Head and Professor of Electrical and Computer Engineering at Polytechnic University, Brooklyn, New York. He holds more than twenty-six patents and is an IEEE Fellow. His research focuses on terabit switches and routers, network security, quality of service control, and optical switching.

Bin Liu, PhD, is Professor in the Department of Computer Science at Tsinghua University, Beijing, China. His research interests include high performance switches and routers, network security, network processors, and traffic engineering. Dr. Liu holds more than ten patents in China.

Table of Contents

Preface

Acknowledgments

Introduction

Architecture of the Internet: Present and Future

Router Architectures

Commercial Core Router Examples

Design of Core Routers

IP Network Management

Outline of the Book

IP Address Lookup

Overview

Trie-Based Algorithms

Hardware-Based Schemes

IPv6 Lookup

Comparison

Packet Classification

Introduction

Trie-Based Classifications

Geometric Algorithms

Heuristic Algorithms

TCAM-Based Algorithms

Traffic Management

Quality of Service

Integrated Services

Differentiated Services

Traffic Policing and Shaping

Packet Scheduling

Buffer Management

Basics of Packet Switching

Fundamental Switching Concept

Switch Fabric Classification

Buffering Strategy in Switching Fabrics

Multiplane Switching and Multistage Switching

Performance of Basic Switches

Shared-Memory Switches

Linked List Approach

Content Addressable Memory Approach

Space-Time-Space Approach

Scaling the Shared-Memory Switches

Multicast Shared-Memory Switches

Input-Buffered Switches

Scheduling in VOQ-Based Switches

Maximum Matching

Maximal Matching

Randomized Matching Algorithms

Frame-based Matching

Stable Matching with Speedup

Banyan-Based Switches

Banyan Networks

Batcher-Sorting Network

Output Contention Resolution Algorithms

The Sunshine Switch

Deflection Routing

Multicast Copy Networks

Knockout-Based Switches

Single-Stage Knockout Switch

Channel Grouping Principle

Two-Stage Multicast Output-Buffered ATM Switch (MOBAS)

Appendix

The Abacus Switch

Basic Architecture

Multicast Contention Resolution Algorithm

Implementation of Input Port Controller

Performance

ATM Routing and Concentration (ARC) Chip

Enhanced Abacus Switch

Abacus Switch for Packet Switching

Crosspoint Buffered Switches

Combined Input and Crosspoint Buffered Switches

Combined Input and Crosspoint Buffered Switches with VOQ

OCF_OCF: Oldest Cell First Scheduling

LQF_RR: Longest Queue First and Round-Robin Scheduling in CIXB-1

MCBF: Most Critical Buffer First Scheduling

CLOS-Network Switches

Routing Property of Clos Network Switches

Looping Algorithm

m-Matching Algorithm

Euler Partition Algorithm

Karol's Algorithm

Frame-Based Matching Algorithm for Clos Network (f-MAC)

Concurrent Matching Algorithm for Clos Network (c-MAC)

Dual-Level Matching Algorithm for Clos Network (d-MAC)

The ATLANTA Switch

Concurrent Round-Robin Dispatching (CRRD) Scheme

The Path Switch

Multi-Plane Multi-Stage Buffered Switch

TrueWay Switch Architecture

Packet Scheduling

Stage-To-Stage Flow Control

Port-To-Port Flow Control

Performance Analysis

Prototype

Load-Balanced Switches

Birkhoff-Von Neumann Switch

Load-Balanced Birkhoff-von Neumann Switches

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