Influence of Temperature on Microelectronics and System Reliability: A Physics of Failure Approach

by Lall; Pradeep

• ISBN13: 9780849394508
• ISBN10: 0849394503
• Edition: 1st
• Format: Hardcover
• Copyright: 1997-04-24
• Publisher: CRC Press

Summary

This new book raises the level of understanding of thermal design criteria. It provides the design team with sufficient knowledge to help them evaluate device architecture trade-offs & the effects of operating temperatures. The book provides the reader a sound scientific basis for system operation at realistic steady state temperatures without reliability penalties. Higher temperature performance than is commonly recommended is shown to be cost effective in production for life cycle costs. The microelectronic package considered in the book is assumed to consist of a semiconductor device with first-level interconnects that may be wirebonds, flip-chip, or tape automated bonds; die attach; substrate; substrate attach; case; lid; lid seal; & lead seal. The temperature effects on electrical parameters of both bipolar & MOSFET devices are discussed, & models quantifying the temperature effects on package elements are identified. Temperature-related models have been used to derive derating criteria for determining the maximum & minimum allowable temperature stresses for a given microelectronic package architecture. The first chapter outlines problems with some of the current modeling strategies. The next two chapters present microelectronic device failure mechanisms in terms of their dependence on steady state temperature, temperature cycle, temperature gradient, & rate of change of temperature at the chip & package level. Physics-of-failure based models used to characterize these failure mechanisms are identified & the variabilities in temperature dependence of each of the failure mechanisms are characterized. Chapters 4 & 5 describe the effects of temperature on the performance characteristics of MOS & bipolar devices. Chapter 6 discusses using high-temperature stress screens, including burn-in, for high-reliability applications. The burn-in conditions used by some manufacturers are examined & a physics-of-failure approach is described. The final chapter overviews existing guidelines for thermal derating of microelectronic devices, which presently involve lowering the junction temperature. The reader then learns how to use physics-of-failure models presented in the previous chapters for various failure processes, to evaluate the sensitivity of device life to variations in manufacturing defects, device architecture, temperature, & non-temperature stresses.

Table of Contents

Chapter 1 Temperature as a Reliability Factor	1	(12)
1. Background	1	(1)
2. Activation Energy-based Models	2	(6)
3. Reliability Prediction Methods	8	(4)
4. How Should Design, Thermal Management, and Reliability Engineers Work Together?	12	(1)
5. Summary	12	(1)
Chapter 2 Temperature Dependence of Microelectronic Package Failure Mechanisms	13	(88)
1. Temperature Dependencies of Failure Mechanisms in the Die Metalization	13	(48)
1.1 Corrosion of Metalization and Bond Pads	15	(8)
1.2 Electromigration	23	(19)
1.3 Hillock Formation	42	(1)
1.4 Metalization Migration	43	(2)
1.5 Contact Spiking	45	(1)
1.6 Constraint Cavitation of Conductor Metalization	45	(16)
2. Effect of Hydrogen and Helium Ambients on Metalization vs Temperature	61	(3)
3. Temperature Dependencies of Failure Mechanisms in the Device Oxide	64	(23)
3.1 Slow Trapping (Oxide Charge Trapping and Detrapping)	65	(3)
3.2 Gate Oxide Breakdown	68	(19)
4. Temperature Dependencies of Failure Mechanisms in the Device	87	(8)
4.1 Ionic Contamination	87	(4)
4.2 Second Breakdown	91	(1)
4.3 Forward Second Breakdown	92	(2)
4.4 Surface-charge Spreading	94	(1)
5. Temperature Dependencies of Failure Mechanisms in the Device Oxide Interface	95	(6)
5.1 Hot Electrons	95	(6)
Chapter 3 Temperature Dependence of Microelectronic Package Failure Mechanisms	101	(54)
1. Temperature Dependencies of Failure Mechanisms in the Die and Die/Substrate Attach	101	(11)
1.1 Die Fracture	101	(8)
1.2 Die Thermal Breakdown	109	(1)
1.3 Die and Substrate Adhesion Fatigue	110	(2)
2. Temperature Dependencies of Failure Mechanisms in First-level Interconnections	112	(18)
2.1 Wirebonded Interconnections	113	(13)
2.2 Tape Automated Bonds	126	(4)
2.3 Flip-chip Joints	130	(1)
3. Temperature Dependencies of Failure Mechanisms in the Package Case	130	(9)
3.1 Cracking in Plastic Packages	131	(6)
3.2 Reversion or Depolymerization of Polymeric Bonds	137	(1)
3.3 Whisker and Dendritic Growth	138	(1)
4. Temperature Dependence of Failure Mechanisms in Lid Seals	139	(5)
4.1 Thermal Fatigue of Lid Seal	139	(5)
5. Temperature Dependencies of Failure Mechanisms in Leads and Lead Seals	144	(11)
5.1 Mishandling and Defect-induced Lead-seal Failure	144	(1)
5.2 Post-forming Defect-localized Lead Corrosion	144	(2)
5.3 Stress Corrosion of Leads at the Lead-lead Seal Interface	146	(1)
5.4 Lead Solder-joint Fatigue	146	(9)
Chapter 4 Electrical Parameter Variations in Bipolar Devices	155	(14)
1. Temperature Dependence of Bipolar Junction Transistor Parameters	155	(14)
1.1 Intrinsic Carrier Concentration, Thermal Voltage, and Mobility	155	(7)
1.2 Current Gain	162	(2)
1.3 BJT Inverter Voltage Transfer Characteristic (VTC)	164	(2)
1.4 Collector-Emitter Saturation Voltage	166	(3)
Chapter 5 Electrical Parameter Variations in MOSFET Devices	169	(14)
1. Temperature Dependence of MOSFET Parameters	169	(14)
1.1 Threshold Voltage	169	(2)
1.2 Mobility	171	(12)
Chapter 6 a Physics-of-failure Approach to IC Burn-In	183	(12)
1. Burn-In Philosophy	183	(1)
2. Problems with Present Approach to Burn-In	183	(8)
3. A Physics-of-Failure Approach to Burn-In	191	(4)
3.1 Understanding Steady-state Temperature Effects	191	(4)
Chapter 7 Derating Guidelines for Temperature-tolerant Design of Microelectronic Devices	195	(30)
1. Problems with the Present Approach to Device Derating	195	(3)
1.1 Dependency on Other Thermal Parameters	196	(1)
1.2 Interaction of Thermal and non-Thermal Stresses	197	(1)
1.3 Low Temperature Device Degradation	197	(1)
1.4 Variations in Device Types	197	(1)
2. An Alternative Approach for Thermally Tolerant Design	198	(4)
3. Stress Limits for Failure Mechanisms in Die Metalization	202	(14)
3.1 Corrosion of Die Metalization	202	(2)
3.2 Electromigration	204	(3)
3.3 Hillock Formation	207	(3)
3.4 Metalization Migration	210	(1)
3.5 Constraint Cavitation of Conductor Metalization	211	(5)
4. Stress Limits for Failure Mechanisms in Device Oxide	216	(6)
4.1 Slow Trapping	216	(6)
5. Stress Limits for Failure Mechanisms in the Device	222	(2)
5.1 Ionic contamination	222	(2)
6. Stress Limits for Failure Mechanisms in the Device Oxide Interface	224	(1)
6.1 Hot Electrons	224	(1)
Chapter 8 Derating Guidelines for Temperature-tolerant Design of Electronic Packages	225	(18)
1. Stress Limits for Failure Mechanisms in the Die and Die/substrate Attach	225	(5)
1.1 Die Fracture	225	(3)
1.2 Die Thermal Breakdown	228	(1)
1.3 Die and Substrate Adhesion Fatigue	229	(1)
2. Stress Limits for Failure Mechanisms in First-level Interconnects	230	(9)
2.1 Wirebonded interconnections	230	(5)
2.2 Tape Automated Bonds	235	(3)
2.2 Flip-chip Bonds	238	(1)
3. Stress Limits for Failure Mechanisms in the Package Case	239	(2)
3.1 Cracking in Plastic Packages	239	(1)
3.2 Reversion or depolymerization of polymeric bonds	239	(1)
3.3 Whisker and dendritic growth	240	(1)
3.4 Modular case fatigue failure	240	(1)
4. STRESS LIMITS FOR FAILURE MECHANISMS IN LID SEALS	241	(2)
4.1 Thermal Fatigue of Lid Seal	241	(2)
Chapter 9 Conclusions	243	(14)
1. Steady State Temperature Effects	243	(14)
References	257	(36)
Index	293	(6)
Permissions	299