Integrated Circuit Manufacturability The Art of Process and Design Integration

by de Gyvez, José; Pineda; Pradhan, Dhiraj

• ISBN13: 9780780334472
• ISBN10: 0780334477
• Edition: 1st
• Format: Hardcover
• Copyright: 1998-10-30
• Publisher: Wiley-IEEE Press

Summary

"INTEGRATED CIRCUIT MANUFACTURABILITY provides comprehensive coverage of the process and design variables that determine the ease and feasibility of fabrication (or manufacturability) of contemporary VLSI systems and circuits. This book progresses from semiconductor processing to electrical design to system architecture. The material provides a theoretical background as well as case studies, examining the entire design for the manufacturing path from circuit to silicon. Each chapter includes tutorial and practical applications coverage. INTEGRATED CIRCUIT MANUFACTURABILITY illustrates the implications of manufacturability at every level of abstraction, including the effects of defects on the layout, their mapping to electrical faults, and the corresponding approaches to detect such faults. The reader will be introduced to key practical issues normally applied in industry and usually required by quality, product, and design engineering departments in today's design practices: * Yield management strategies * Effects of spot defects * Inductive fault analysis and testing * Fault-tolerant architectures and MCM testing strategies. This book will serve design and product engineers both from academia and industry. It can also be used as a reference or textbook for introductory graduate-level courses on manufacturing."

Author Biography

About the Editors...JosT Pineda de Gyvez is an associate professor in the Department of Electrical Engineering, holding a joint faculty appointment with the Department of Computer Science, at Texas A&M University. Dr. Pineda de Gyvez was associate editor of technology for IEEE Transactions on Semiconductor Manufacturing and associate editor for cellular neural networks for IEEE Transactions on Circuits and Systems: Part 1.

Table of Contents

Preface	xiii
Chapter 1 Introduction	1	(8)
Jose Pineda de Gyvez
References	7	(2)
Chapter 2 Defect Monitoring and Characterization	9	(34)
Eric Bruls
2.1 Market Developments	9	(1)
2.2 Price	9	(1)
2.3 Quality and Reliability	10	(1)
2.4 IC Manufacturing Defects	11	(10)
2.4.1 IC Development Flow	12	(3)
2.4.2 The Manufacturing Process	15	(4)
2.4.3 Defect Mechanisms	19	(2)
2.5 Defect Monitoring	21	(8)
2.5.1 Global Defects	22	(2)
2.5.2 Local Defects	24	(5)
2.6 Defect Modeling	29	(10)
2.6.1 Global Defects	29	(2)
2.6.2 Local Defects	31	(8)
2.7 Summary	39	(1)
2.8 Exercises	40	(1)
References	41	(2)
Chapter 3 Digital CMOS Fault Modeling and Inductive Fault Analysis	43	(42)
Manoj Sachdev
3.1 Introduction	43	(2)
3.1.1 Quality and Reliability Awareness	44	(1)
3.1.2 Role of Testing in Quality Improvement	44	(1)
3.2 Objectives of Fault Modeling	45	(1)
3.3 Levels of Fault Modeling	46	(19)
3.3.1 Logic-Level Fault Modeling	47	(6)
3.3.2 Transistor-Level Fault Modeling	53	(7)
3.3.3 Layout-Level Fault Modeling	60	(1)
3.3.4 Functional-Level Fault Modeling	60	(1)
3.3.5 Delay Fault Models	61	(2)
3.3.6 Leakage Fault Models	63	(1)
3.3.7 Temporary Faults	64	(1)
3.4 Inductive Fault Analysis	65	(12)
3.4.1 The Defect-Fault Relationship	66	(2)
3.4.2 IC Design and Layout-Related Defect Sensitivity	68	(1)
3.4.3 Basic Concepts of IFA	69	(2)
3.4.4 Practical Experiences with IFA	71	(6)
3.4.5 The IFA: Strengths and Weaknesses	77	(1)
3.5 Summary	77	(1)
References	78	(7)
Chapter 4 Functional Yield Modeling	85	(36)
Gary C. Cheek
Geoff O'Donoghue
4.1 Introduction	85	(1)
4.2 Basic Yield Statistics: Random Defects	86	(8)
4.2.1 Yield Model Derivations	89	(5)
4.3 Classes of Yield Models	94	(5)
4.3.1 Class I Yield Models	94	(1)
4.3.2 Class II Yield Models	95	(1)
4.3.3 Class III Yield Models	96	(3)
4.3.4 Class IV Yield Models	99	(1)
4.4 Yield Model Components	99	(9)
4.4.1 Defect Density Term in Yield Models	100	(3)
4.4.2 Area Term in Yield Models	103	(1)
4.4.3 Probability of Fail	104	(2)
4.4.4 Computation of Critical Area	106	(1)
4.4.5 The Y(0) Term in Yield Models	107	(1)
4.5 Applications of Functional Yield Models	108	(7)
4.5.1 Low-Yield Cutoff and Chip Costing	109	(1)
4.5.2 Spatial Yield Distributions: Y(0)	110	(1)
4.5.3 Yield Distributions	110	(1)
4.5.4 Critical Area in Product Design: SRAM Example	111	(2)
4.5.5 Critical Area in Yield Calculation	113	(1)
4.5.6 Use of Yield Models for Scaling Applications	113	(1)
4.6 Summary	115	(1)
4.7 Exercises and Solutions	115	(3)
References	118	(3)
Chapter 5 Critical Area and Fault Probability Prediction	121	(36)
D.M.H. Walker
5.1 Introduction	121	(3)
5.2 Theoretical Background	124	(1)
5.3 Contamination to Defect Mapping	125	(1)
5.4 Defect to Fault Mapping	126	(12)
5.4.1 Geometrical Methods	126	(6)
5.4.2 Monte Carlo Methods	132	(3)
5.4.3 Combined Methods	135	(1)
5.4.4 Three-Dimensional Defects	136	(1)
5.4.5 Spatial Clustering Within Chips	137	(1)
5.4.6 Circuit Model Issues	137	(1)
5.5 Hierarchical Defect to Fault Mapping	138	(4)
5.5.1 Identification of Nonoverlapping Layout Areas	139	(1)
5.5.2 Hierarchical Circuit Extraction of Nonoverlapping Layout	140	(1)
5.5.3 Hierarchical Defect to Fault Mapping of Nonoverlapping Layout	141	(1)
5.5.4 Global Fault Reporting	141	(1)
5.6 Fault to Failure Mapping	142	(1)
5.7 Applications	142	(4)
5.7.1 Yield Prediction	142	(1)
5.7.2 Redundancy Analysis	143	(1)
5.7.3 Test Generation	144	(1)
5.7.4 Process Diagnosis and Monitoring	144	(1)
5.7.5 Design for Manufacturability	145	(1)
5.8 Summary and Research Directions	146	(1)
5.9 Exercises and Solutions	147	(1)
References	148	(9)
Chapter 6 Statistical Methods of Parametric Yield and Quality Enhancement	157	(60)
Maciej Styblinski
6.1 Problems and Methodologies of Statistical Circuit Design	158	(1)
6.2 Circuit Variables, Parameters, and Performances	158	(3)
6.2.1 Designable Parameters	159	(1)
6.2.2 Random Variables	159	(1)
6.2.3 Circuit (Simulator) Variables	159	(1)
6.2.4 Circuit Performance	160	(1)
6.3 Statistical Modeling of Circuit (Simulator) Variables	161	(5)
6.3.1 Passive Discrete RLC Elements	161	(1)
6.3.2 Passive Integrated RLC Elements	162	(1)
6.3.3 Single Active Device Modeling for Discrete and Integrated Circuits	162	(2)
6.3.4 Global and Local (Mismatch) Models for Integrated Circuits	164	(2)
6.4 Acceptability Regions	166	(5)
6.4.1 Methods of Acceptability Region Approximation	168	(3)
6.5 Parametric Yield	171	(4)
6.6 Indirect Methods of Yield Enhancement	175	(5)
6.6.1 Simplicial Approximation-Based Design Centering	176	(1)
6.6.2 Worst-Case Distance-Driven Design Centering	177	(1)
6.6.3 Performance Space-Oriented Design Centering	178	(2)
6.7 Statistical Methods of Yield Optimization	180	(21)
6.7.1 Problem Classification	180	(1)
6.7.2 Large-Sample versus Small-Sample Methods	181	(1)
6.7.3 Using Standard Deterministic Optimization Algorithms	182	(1)
6.7.4 Large-Sample Heuristic Methods for Discrete Circuits	183	(1)
6.7.5 Large-Sample, Derivative-Based Methods for Discrete Circuits	184	(4)
6.7.6 Large-Sample, Derivative-Based Method for Integrated Circuits	188	(3)
6.7.7 Small-Sample, Stochastic Approximation-Based Methods for Discrete Circuits	191	(5)
6.7.8 Small-Sample, Stochastic Approximation Methods for Integrated Circuits	196	(3)
6.7.9 Case Study: Process Optimization for Manufacturing Yield Enhancement	199	(2)
6.8 Design for Quality	201	(9)
6.8.1 Generalized Formulation of Yield, Variability, and Taguchi Circuit Optimization Problems	202	(3)
6.8.2 Propagation of Variance Method	205	(5)
6.9 Conclusion	210	(1)
References	210	(7)
Chapter 7 Architectural Fault Tolerance	217	(52)
S.K. Tewksbury
7.1 Introduction	217	(6)
7.1.1 Use of Known-Faulty Components When Manufacturing an Electronic System	218	(1)
7.1.2 Large-Area Integrated Circuits	219	(1)
7.1.3 In-Service Failures	220	(1)
7.1.4 Difficulty of Repair	221	(1)
7.1.5 Selective Fault Tolerance	221	(2)
7.2 Local Fault Tolerance	223	(11)
7.2.1 Modular Redundancy	223	(4)
7.2.2 Error Correcting Codes	227	(5)
7.2.3 Algorithm-Based Fault Tolerance	232	(2)
7.3 Global Reconfiguration	234	(14)
7.3.1 Reconfigurable Arrays of Computation Cells	235	(6)
7.3.2 Two-Dimensional Arrays	241	(2)
7.3.3 Self-Reconfiguration Algorithms for Two-Dimensional Arrays	243	(3)
7.3.4 Replacement of Full Rows (Columns) by Spare Rows (Columns)	246	(2)
7.4 Physical Switch Technologies for Reconfiguration	248	(12)
7.4.1 Electronically Programmable Reconfiguration	249	(6)
7.4.2 Physical Restructuring of Interconnections	255	(5)
7.5 Summary	260	(1)
References	260	(9)
Chapter 8 Design for Test and Manufacturability	269	(18)
Dhiraj Pradhan
Adit Singh
8.1 Introduction	269	(1)
8.1.1 The Basic Problems of Testing	269	(1)
8.2 Testing for Stuck-at Faults	270	(4)
8.2.1 Limitations of the Stuck-at Fault Model	272	(2)
8.3 Test Coverage and Defect Levels	274	(2)
8.4 Quality Screening Based on Defect Clustering	276	(8)
8.4.1 Binning for Low Defect Levels	277	(1)
8.4.2 Analysis	278	(3)
8.4.3 Test Transparency Function	281	(2)
8.4.4 Numerical Results	283	(1)
8.5 Applications	284	(1)
References	285	(2)
Chapter 9 Testing Solutions for MCM Manufacturing	287	(18)
Yervant Zorian
9.1 Introduction	287	(2)
9.2 MCM Testing Problem	289	(4)
9.2.1 Wafer and Bare Die Test	290	(2)
9.2.2 Substrate Testing	292	(1)
9.2.3 MCM Assembly Testing and Repair	292	(1)
9.3 A Structured Testability Approach	293	(5)
9.3.1 The Bare Dies Test Procedure	294	(1)
9.3.2 The Assembled MCM Test and Diagnosis Procedure	294	(4)
9.4 Chip-Level Structured Testability Inclusion	298	(2)
9.5 Module-Level Testability Needs	300	(1)
9.6 Conclusion	301	(1)
References	301	(4)
Index	305	(10)
About the Editors	315