Interconnect-Centric Design for Advanced SOC and NOC

by Nurmi, Jari; Tenhunen, Hannu; Isoaho, Jouni; Jantsch, Axel

• ISBN13: 9781402078354
• ISBN10: 1402078358
• Format: Hardcover
• Copyright: 2004-08-01
• Publisher: Kluwer Academic Pub

Summary

In Interconnect-centric Design for Advanced SoC and NoC , we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

Table of Contents

Preface	vii
Part I PHYSICAL AND ELECTRICAL ISSUES
1 Communication-based Design for Network-on-Chip	3	(22)
Jan Rabaey
2 Wires as Interconnects	25	(30)
Li-Rong Zheng and Hannu Tenhunen
3 Global Interconnect Analysis	55	(30)
Tero Nurmi, Li-Rong Zheng, Jian Liu, Tapani Ahonen, Dinesh Pamunuwa, Jouni Isoaho and Hannu Tenhunen
4 Design Methodologies for On-Chip Inductive Interconnect	85	(40)
Magdy Ali El-Moursy and Eby Friedman
5 Clock Distribution for High-Performance Designs	125	(30)
Stefan Rusu
Part II LOGICAL AND ARCHITECTURAL ISSUES
6 Error-Tolerant Interconnect Schemes	155	(22)
Heilco Zimmer and Axel Jantsch
7 Power Reduction Coding for Buses	177	(30)
Paul P. Sotiriadis
8 Bus Structures in Networks-on-Chip	207	(24)
Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna and Timo D. Hämäläinen
9 From Buses to Networks	231	(22)
David Sigüenza Tortosa and Jari Nurmi
10 Arbitration and Routing Schemes for On-Chip Packet Networks	253	(32)
Heikki Kariniemi and Jari Nurmi
Part III DESIGN METHODOLOGY AND TOOLS
11 Self-Timed Approach for Noise Reduction in NoC	285	(30)
Pasi Liljeberg, Johanna Tuominen, Sampo Tuuna, Juha Plosila and Jouni Isoaho
12 Formal Communication Modelling and Refinement	315	(26)
Juha Plosila, Tiberius Seceleanu and Kaisa Sere
13 Network Centric System-Level Model for Multiprocessor System-on-Chip Simulation	341	(26)
Jan Madsen, Shankar Mahadevan and Kashif Virk
14 Socket-based Design Techniques using Decoupled Interconnects	367	(32)
Drew Wingard
Part IV APPLICATION CASES
15 Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV	399	(26)
Kees Goossens, Om Prakash Gangwal, Jens Röver and A.P. Niranjan
16 A Brunch from the Coffee Table - Case Study in NOC Platform Design	425
Tapani Ahonen, Seppo Virtanen, Juha Kylliäinen, Dragos Truscan, Tuukka Kasanko, David Sigüenza-Tortosa, Tapio Ristimäki, Jani Paakkulainen, Tero Nurmi, Ilkka Saastamoinen, Hannu Isännäinen, Johan Lilius, Jari Nurmi and Jouni Isoaho