Introduction to Digital Systems

by Milos D. Ercegovac (Univ. of California Los Angeles); Tomá; s Lang (Univ. of California at Irvine); Jaime H. Moreno (IBM T. J. Watson Research Center)

• ISBN13: 9780471527992
• ISBN10: 0471527998
• Edition: CD
• Format: Hardcover
• Copyright: 1998-10-01
• Publisher: Wiley

Summary

A basic grounding in one of today's quickly evolving technologies. To gain one's bearing in the whirlwind of rapid development in the digital theory arena, getting a firm grasp of the basics is vital. This book provides a solid foundation in the elements of basic digital electronic and switching theory. Down to earth, yet scholarly in approach, it builds on theory with discussions of real-world digital components, design methodologies, and tools. A companion Web site provides additional information.

Table of Contents

PREFACE	v
1 INTRODUCTION	1	(11)
1.1 About digital systems	1	(5)
1.2 Specification and implementation, analysis, and design	6	(4)
1.3 Computer-aided design tools	10	(1)
1.4 Further readings	11	(1)
2 SPECIFICATION OF COMBINATIONAL SYSTEMS	12	(48)
2.1 Combinational systems: definition and specification levels	12	(2)
2.2 High-level specification of combinational systems	14	(2)
2.3 Data representation and coding	16	(4)
2.3.1 Representation of characters	17	(1)
2.3.2 Representation of positive integers	17	(4)
2.4 Binary specification of combinational systems	21	(16)
2.4.1 Switching functions	22	(4)
2.4.2 Switching expressions	26	(11)
2.5 Examples of specifications	37	(2)
2.6 Specification using MuVHDL	39	(13)
2.7 Further readings	52	(1)
Exercises	52	(8)
3 COMBINATIONAL INTEGRATED CIRCUITS: CHARACTERISTICS AND CAPABILITIES	60	(28)
3.1 Representation of binary variables	61	(1)
3.2 Structure and operation of CMOS gates	62	(6)
3.2.1 n-type and p-type switches	62	(1)
3.2.2 NOT gate	63	(1)
3.2.3 NAND and NOR gates	64	(1)
3.2.4 AND and OR gates	65	(1)
3.2.5 Complex gates	65	(2)
3.2.6 Transmission gate, XOR gate, and two-input multiplexer	67	(1)
3.3 Propagation delays, transition times, and effect of load	68	(3)
3.4 Voltage variations and noise margins	71	(1)
3.5 Power dissipation and delay-power product	71	(1)
3.6 Buses and three-state drivers	72	(2)
3.7 Circuit characteristics of a CMOS family	74	(1)
3.8 Evolution in the implementation of digital systems	74	(3)
3.9 VLSI circuit-level design styles	77	(1)
3.10 Packaging level: chips, boards, and cabinets	78	(1)
3.11 Mu VHDL description of gates	78	(5)
3.12 Further readings	83	(1)
Exercises	84	(4)
4 DESCRIPTION AND ANALYSIS OF GATE NETWORKS	88	(24)
4.1 Definition of gate networks	89	(1)
4.2 Description and characteristics of gate networks	90	(2)
4.3 Sets of gates	92	(2)
4.4 Analysis of gate networks	94	(9)
4.5 Description of gate networks using Mu VHDL	103	(2)
4.6 Further readings	105	(1)
Exercises	106	(6)
5 DESIGN OF COMBINATIONAL SYSTEMS: TWO-LEVEL GATE NETWORKS	112	(32)
5.1 Minimal two-level networks	115	(1)
5.2 Karnaugh maps	116	(5)
5.3 Minimization of sum of products and product of sums	121	(10)
5.3.1 Sum of products	121	(5)
5.3.2 Product of sums	126	(1)
5.3.3 Examples of design of minimal two-level gate network	127	(2)
5.3.4 Tabular methods	129	(2)
5.4 Design of multiple-output two-level gate networks	131	(3)
5.5 Two-level NAND-NAND and NOR-NOR networks	134	(1)
5.6 Limitations of two-level networks	135	(1)
5.7 Programmable modules: PLAS and PALS	136	(5)
5.8 Further readings	141	(1)
Exercises	142	(2)
6 DESIGN OF COMBINATIONAL SYSTEMS: MULTILEVEL GATE NETWORKS	144	(17)
6.1 Typical transformations to meet network requirements	145	(7)
6.2 Alternative implementations	152	(2)
6.3 Networks with XOR and XNOR gates	154	(1)
6.4 Networks with two-input multiplexers	155	(3)
6.5 Further readings	158	(1)
Exercises	159	(2)
7 SPECIFICATION OF SEQUENTIAL SYSTEMS	161	(34)
7.1 Synchronous sequential systems	161	(6)
7.1.1 Synchronous and asynchronous systems	162	(1)
7.1.2 State description of finite state systems	163	(3)
7.1.3 Mealy and Moore machines	166	(1)
7.2 Representation of the state transition and output functions	167	(3)
7.2.1 State diagram	167	(2)
7.2.2 State names	169	(1)
7.3 Time behavior and finite state machines	170	(3)
7.3.1 Input-output sequence pairs from state description	170	(1)
7.3.2 State description from time behavior	171	(2)
7.4 Finite memory sequential systems	173	(1)
7.5 Controllers	173	(1)
7.6 Equivalent sequential systems and minimization of the number of states	174	(8)
7.6.1 State description with redundant states	176	(1)
7.6.2 Equivalent systems	177	(1)
7.6.3 Procedure to minimize the number of states	178	(4)
7.7 Binary specification of sequential systems	182	(1)
7.8 Specification of different types of sequential systems	183	(3)
7.9 Specification of sequential systems in MnVHDL	186	(3)
7.10 Further readings	188	(1)
Exercises	189	(6)
8 SEQUENTIAL NETWORKS	195	(46)
8.1 Canonical form of sequential networks	195	(2)
8.2 High-level and binary implementations	197	(1)
8.3 Gated latch and D flip-flop	198	(7)
8.4 Timing characteristics of sequential networks	205	(4)
8.5 Analysis of canonical sequential networks	209	(3)
8.6 Design of canonical sequential networks	212	(2)
8.7 Other flip-flop modules: SR, JK, and T	214	(2)
8.8 Analysis of networks with flip-flop	216	(5)
8.9 Design of networks with flip-flops	221	(5)
8.10 Design using special state assignments	226	(3)
8.11 Description of flip-flops and sequential networks with MuVHDL	229	(5)
8.11.1 Description of flip-flops	229	(4)
8.11.2 Description of flip-flop networks	233	(1)
8.12 Further readings	234	(1)
Exercises	235	(6)
9 STANDARD COMBINATIONAL MODULES	241	(36)
9.1 Binary decoders	241	(9)
9.1.1 Binary decoder and OR gate as universal set	245	(1)
9.1.2 Decoder networks	246	(4)
9.2 Binary encoders	250	(4)
9.3 Priority encoders	254	(3)
9.4 Multiplexers (selectors)	257	(5)
9.4.1 Multiplexer as universal combinational module	259	(2)
9.4.2 Multiplexer trees	261	(1)
9.5 Demultiplexers (distributors)	262	(2)
9.6 Shifters	264	(5)
9.7 Implementation of modules	269	(1)
9.8 Further readings	270	(1)
Exercises	270	(7)
10 ARITHMETIC COMBINATIONAL MODULES AND NETWORKS	277	(34)
10.1 Adder modules for positive integers	278	(8)
10.2 Networks of adder modules	286	(2)
10.3 Representation of signed integers and basic operations	288	(10)
10.3.1 Representation and sign detection	288	(4)
10.3.2 Addition and subtraction of signed integers	292	(6)
10.4 ALU modules and networks	298	(2)
10.5 Comparator modules	300	(2)
10.6 Multipliers	302	(2)
10.7 Example of networks with standard arithmetic modules	304	(2)
10.8 Further readings	306	(1)
Exercises	306	(5)
11 STANDARD SEQUENTIAL MODULES	311	(28)
11.1 Registers	311	(3)
11.2 Shift registers	314	(5)
11.3 Counters	319	(13)
11.4 Multimodule systems	332	(1)
11.5 Further readings	333	(1)
Exercises	334	(5)
12 PROGRAMMABLE MODULES	339	(23)
12.1 Programmable sequential arrays (PSA)	340	(3)
12.2 Read-only memories (ROM)	343	(4)
12.3 Networks of programmable modules	347	(2)
12.4 Advantages and disadvantages of programmable modules	349	(1)
12.5 Field-programmable gate arrays (FPGAS)	350	(8)
12.6 Further readings	358	(1)
Exercises	358	(4)
13 REGISTER-TRANSFER LEVEL (RTL) SYSTEMS	362	(36)
13.1 Execution graphs	362	(4)
13.2 Organization of systems	366	(4)
13.3 Specification of RTL systems using MuVHDL	370	(2)
13.4 Implementation of RTL systems	372	(4)
13.5 Analysis of RTL systems	376	(5)
13.6 Design of RTL systems	381	(1)
13.7 Further readings	392	(1)
Exercises	392	(6)
14 DATA AND CONTROL SUBSYSTEMS	398	(38)
14.1 Data subsystem	398	(7)
14.1.1 Storage modules	399	(3)
14.1.2 Functional modules	402	(1)
14.1.3 Datapaths	403	(2)
14.2 Control subsystem	405	(4)
14.3 A design example	409	(3)
14.4 Microprogrammed controller	412	(14)
14.4.1 Structure of a microprogrammed controller	414	(2)
14.4.2 Microinstruction format	416	(5)
14.4.3 Example of microprogrammed system	421	(1)
14.4.4 Microinstruction Timing	420	(1)
14.4.5 Example of microprogrammed system	421	(5)
14.5 Further readings	426	(1)
Exercises	426	(10)
15 SPECIFICATION AND IMPLEMENTATION OF A MICROCOMPUTER	436	(44)
15.1 Basic components of a computer	437	(2)
15.2 Specification (architecture) of a simple microcomputer system	439	(18)
15.2.1 Memory subsystem	441	(3)
15.2.2 Input/output (I/O) subsystem	444	(1)
15.2.3 Processor	445	(1)
15.2.4 Specification of the memory contents	456	(1)
15.3 Implementation of a simple microcomputer system	457	(7)
15.3.1 Memory subsystem	457	(1)
15.3.2 Processor	458	(6)
15.4 Operation of the computer and cycle time	464	(4)
15.5 Description of the processor implementation in MuVHDL	468	(9)
15.5.1 Structure of processor	468	(1)
15.5.2 Data subsystem	469	(1)
15.5.3 Register file	470	(1)
15.5.4 Arithmetic-logic unit	471	(1)
15.5.5 Registers	472	(1)
15.5.6 Other modules in the data subsystem	472	(1)
15.5.7 Control subsystem	473	(4)
15.6 Further readings	477	(1)
Exercises	478	(2)
APPENDIX: BOOLEAN ALGEBRAS	480	(9)
A.1 Boolean algebra	480	(1)
A.2 Switching algebra	481	(1)
A.3 Important theorems in Boolean algebra	482	(4)
A.4 Other examples of Boolean algebras	486	(1)
A.5 Further readings	487	(2)
INDEX	489