Layout Optimization in Vlsi Design

by Lu, Bing; Du, Dingzhu; Sapatnekar, Sachin S.; Lu, Bing

• ISBN13: 9781402000898
• ISBN10: 1402000898
• Format: Hardcover
• Copyright: 2002-02-01
• Publisher: Springer Verlag

Summary

The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interconnect delay, noise, crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout optimization problems emerging with the advent of very deep submicron technologies in semiconductor processing. Audience: A reference work for graduate students, senior undergraduates, and researchers.

Table of Contents

Preface	vii
Integrated Floorplanning and Interconnect Planning	1	(18)
H.-M. Chen
Martin D.F. Wong
H. Zhou
F. Y. Young
H. H. Yang
N. Sherwani
Interconnect Planning	19	(26)
J. Cong
Modern Standard-cell Placement Techniques	45	(44)
X. Yang
E. Bozorgzadeh
M. Sarrafzadeh
M. Wang
Non-Hanan Optimization for Global VLSI Interconnect	89	(36)
J. Hu
S. S. Sapatnekar
Techniques for Timing-Driven Routing	125	(30)
J. Lillis
Interconnect Modeling and Design with Consideration of Inductance	155	(36)
L. He
Modeling and Characterization of IC Interconnects and Packagings for the Signal Intergrity Verification on High-Performance VLSI Circuits	191	(70)
Y. Eo
Tradeoffs in Digital Binary Adder Design: the Effects of Floorplanning, Number of Levels of Metals, and Supply Voltage on Performance and Area	261
V. Kantabutra
S. Perri
P. Corsonello