Low-power High-resolution Analog to Digital Converters

by Zjajo, Amir; Pineda De Gyvez, Jose

• ISBN13: 9789048197248
• ISBN10: 9048197244
• Edition: 1st
• Format: Hardcover
• Copyright: 2010-12-10
• Publisher: Springer Verlag

Summary

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods.In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

Table of Contents

Introduction	p. 1
A/D Conversion Systems	p. 1
Remarks on Current Design and Debugging Practice	p. 5
Motivation	p. 9
Organization	p. 9
Analog to Digital Conversion	p. 11
High-Speed High-Resolution A/D Converter Architectural Choices	p. 11
Multi-Step A/D Converters	p. 11
Pipeline A/D Converteres	p. 13
Parallel Pipelined A/D Converters	p. 14
A/D Converters Realization Comparison	p. 16
Notes on Low Voltage A/D Converter Design	p. 20
A/D Converter Building Blocks	p. 25
Sample-and-Hold	p. 25
Operational Amplifier	p. 29
Latched Comparators	p. 33
A/D Converters: Summary	p. 39
Design of Multi-Step Analog to Digital Converters	p. 41
Multi-Step A/D Converter Architecture	p. 41
Design Considerations for Non-Ideal Multi-Step A/D Converter	p. 44
Time-Interleaved Front-End Sample-and-Hold Circuit	p. 49
Time-Interleaved Architecture	p. 49
Matching of Sample-and-Hold Unites	p. 55
Circuit Design	p. 62
Multi-Step A/D Converter Stage Design	p. 67
Coarse Quantization	p. 67
Fine Quantization	p. 74
Inter-Stage Design and Calibration	p. 85
Sub-D/A Converter Design	p. 85
Residue Amplifier	p. 87
Experimental Results	p. 93
Conclusions	p. 102
Multi-Step Analog to Digital Converter Testing	p. 103
Analog ATPG for Quasi-Static Structural Test	p. 103
Test Strategy Definition	p. 105
Linear Fault Model Based on Quasi-Static Nodal Voltage Approach	p. 106
Decision Criteria and Test-Stimuli Optimization	p. 117
Design for Testability Concept	p. 124
Power-Scan Chain DfT	p. 126
Application Example	p. 132
On-Chip Stimulus Generation for BIST Applications	p. 141
Continuous-and Discrete-Time Circuit Topologies	p. 143
Design of Continuous-and Discrete-Time Waveform Generator	p. 153
Remarks on Built-In Self-Test Concepts	p. 163
Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs	p. 169
Stochastic MNA for Process Variability Analysis	p. 170
Stochastic MNA for Noise Analysis	p. 173
Application Example	p. 176
Conclusion	p. 179
Multi-Step Analog to Digital Converter Debugging	p. 183
Concept of Sensor Networks	p. 183
Observation Strategy	p. 184
Integrated Sensor	p. 186
Decision Window and Application Limits	p. 190
Die-Level Process Monitors Circuit Design	p. 194
Temperature Sensor	p. 201
Estimation of Die-Level Process Variations	p. 205
Expectation-Maximization Algorithm	p. 205
Support Vector Machine Limits Estimator	p. 208
Debugging of Multi-Step A/D Converter Stages	p. 210
Quality Criterion	p. 211
Estimation Method	p. 213
DfT for Full Accessability of Multi-Step Converters	p. 218
Test Control Block	p. 221
Analog Test Control Block	p. 222
Debugging of Time-Interleaved Systems	p. 211
Foreground Calibration	p. 231
Experimental Results	p. 235
Application of Results for A/D Test Window Generation/Update	p. 239
Application of Results for A/D Converter Debugging and Calibration	p. 244
Conclusion	p. 250
Conclusions and Recommendations	p. 253
Summary of Results	p. 253
Recommendations and Future Research	p. 255
Appendix	p. 257
References	p. 267
Index	p. 269
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