Low-Voltage Low-Power Digital Bicmos Circuits: Circuit Design, Comparative Study, and Sensitivity Analysis

by Rofail, Samir S.; Seng, Yeo Kiat; Rofail, Samir S.; Yeo, Kiat Seng

• ISBN13: 9780130113801
• ISBN10: 0130113808
• Format: Hardcover
• Copyright: 1999-07-01
• Publisher: PRENTICE HALL

Summary

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Table of Contents

Preface	ix
Acknowledgments	xi
Nomenclature	xiii
Introduction	1	(26)
Why Low-Voltage, Low-Power?	2	(2)
Why BiCMOS Technology?	4	(3)
Applications of BiCMOS	7	(3)
Random Access Memories (RAMs)	7	(2)
Digital Signal Processing (DSP)	9	(1)
Telecommunications Applications	9	(1)
Low-Voltage Low-Power Design	10	(11)
Low-Voltage Low-Power Design Limitations	10	(3)
Power Dissipation of a Single Logic Gate	13	(1)
Power Dissipation of LSIs	14	(1)
Techniques of Reducing the Power Dissipation	15	(2)
Future BiCMOS Directions	17	(4)
Conclusions	21	(1)
References	21	(6)
BiCMOS Process Technology	27	(56)
Introduction	27	(1)
Bipolar and CMOS Processes Convergence	28	(2)
CMOS Processing Issues of the Twin-Well BiCMOS Process	30	(3)
Various Source/Drain Structures and the Channel Profiles	30	(3)
Threshold Voltage Issues	33	(1)
Bipolar Process Techniques	33	(6)
Base Design Techniques	36	(1)
Collector Design Techniques	37	(1)
Emitter Design Techniques	38	(1)
BiCMOS Isolation Issues	39	(5)
Latch-up Phenomenon	39	(1)
Trench Isolation	40	(2)
Epitaxial Layer	42	(1)
Buried Layers	43	(1)
Active Device Isolation	43	(1)
BiCMOS Interconnect Issues	44	(6)
Silicidation	44	(2)
Local Interconnect	46	(2)
Metallization and Planarization	48	(2)
Classification of BiCMOS Technologies	50	(15)
Process Flow of a High-Performance 5 V, 0.8 μm Digital BiCMOS	50	(6)
Process Changes for the 0.5 μm Digital BiCMOS Technology	56	(4)
An Analog/Digital BiCMOS Process Flow	60	(5)
A New Low-Power Ultra Low-Capacitance BiCMOS Process	65	(3)
Process Description	66	(1)
Shallow Trench Isolation (STI)	66	(2)
Manufacturing Considerations	68	(1)
Future Trends in BiCMOS Technology	68	(5)
Bipolar Device Structure Improvements	69	(3)
Silicon-On-Insulator (SOI) Technology	72	(1)
Conclusions	73	(2)
References	75	(8)
MOS Device Modeling	83	(48)
The Threshold Voltage Models	83	(4)
The MOSFET Current Models	87	(9)
The MOSFET in a Hybrid Mode Environment	96	(28)
Surface P-Channel for Sub-Half Micron Devices	97	(3)
Device Fabrication	100	(1)
Model Parameters Extraction	100	(2)
Sub-Half Micron DC Model Formulation	102	(22)
Concluding Remarks	124	(1)
Summary	125	(1)
References	126	(5)
Low-Voltage BiCMOS Digital Circuits	131	(180)
Introduction	131	(1)
Source-Well Tie and Quasi-Reduction of Bipolar Turn-On Voltage Techniques	132	(8)
pMOS/NPN Pull-Down Technique With and Without Source-Well Tie	132	(4)
Quasi-Reduction of Bipolar Turn-On Voltage Technique	136	(4)
Full-Swing BiCMOS Logic Circuits with Complementary Emitter-Follower Driver Configuration	140	(26)
Introduction	140	(7)
BiCMOS Driver Configurations	147	(2)
Full-Swing Techniques	149	(1)
Comparison Between the Three Different Driver Configurations	150	(3)
Full-Swing Complementary MOS/Bipolar Logic (FS-CMBL) Circuits	153	(2)
Experimental Results and Analysis	155	(1)
Circuit Variations of the FS-CMBL with Feedback	156	(4)
Experimental Results and Analysis	160	(6)
Merged BiCMOS (MBiCMOS) Logic Gates	166	(11)
Introduction	166	(1)
MBiCMOS Gate	167	(2)
Circuit Performance and Comparison	169	(3)
Experimental Tests and Analysis	172	(3)
Simulation Results and Analysis	175	(2)
Full-Swing MBiCMOS Gate	177	(1)
Full Voltage Swing Multi-Drain/Multi-Collector Complementary BiCMOS Buffers	177	(12)
Introduction	177	(1)
Conventional BiCMOS and CBiCMOS Buffers	178	(1)
Multi-Drain/Multi-Collector BiCMOS Buffers	179	(2)
Simulation Results and Discussion	181	(2)
Full-Swing Multi-Drain/Multi-Collector BiCMOS Buffers	183	(1)
Circuit Implementation and Operation	184	(1)
Simulation Results and Discussion	185	(4)
Quasi-Complementary BiCMOS Logic Circuits	189	(19)
Introduction	189	(1)
Circuit Concept of the QC-BiCMOS and Its Advantages	190	(3)
Circuit Performance Comparison and Analysis	193	(8)
Delay Analysis	201	(3)
Design Issues	204	(1)
Experimental Results	204	(2)
Appendix	206	(2)
Full-Swing Schottky BiCMOS/BiNMOS Logic Circuits	208	(15)
Introduction	208	(1)
Basic Concept	208	(2)
Circuit Implementations	210	(2)
Circuit Simulation and Discussion	212	(5)
Scaling the Supply Voltage	217	(1)
Delay Dependence on the Frequency of Operation	218	(1)
Power Dissipation	219	(2)
Area Comparison	221	(1)
Crossover Capacitance	222	(1)
Feedback-Type BiCMOS Logic Circuits	223	(35)
Introduction	223	(1)
Conventional BiCMOS Circuits and Their Limitations	223	(1)
R + N Type and Feedback-Type (FB) BiCMOS Logic Gates	224	(6)
BiCMOS Full-Swing Circuits Utilizing a Positive Capacitively Coupled Feedback Technique	230	(14)
1.2 V Complementary Feedback BiCMOS Logic Gates	244	(8)
1.5 V BiCMOS Dynamic Logic Circuit	252	(6)
High-Beta BiCMOS (Hβ-BiCMOS) Logic Circuits	258	(11)
Introduction	258	(1)
Hβ-BiCMOS Logic Circuit	258	(3)
Circuit Operation of the Hβ-BiCMOS Circuit	261	(1)
Circuit Simulations and Discussion	262	(2)
A BiCMOS Charge Pump with Hβ-BiCMOS	264	(5)
Transiently Saturated Full-Swing BiCMOS (TS-FS-BiCMOS) Logic Circuits	269	(10)
Introduction	269	(1)
Circuit Concept and Operation	269	(3)
Circuit Performance Comparison and Analysis	272	(4)
Design Issues	276	(2)
Experimental Results and Analysis	278	(1)
Bootstrapped BiCMOS Logic Circuits	279	(26)
Introduction	279	(2)
1.5 V Bootstrapped BiCMOS Logic Gate (BS-BiCMOS)	281	(2)
Bootstrapped Full-Swing BiCMOS/BiNMOS Inverter	283	(14)
Double Bootstrapped BiCMOS Logic Gates (DB-BiCMOS)	297	(8)
References	305	(6)
Delay Time and Power Dissipation Sensitivity Analyses of Multi-Generation BiCMOS Digital Circuits	311	(32)
Introduction	311	(1)
Relationship Between Key BJT/MOS Process and Device/Circuit Parameters	312	(1)
Sensitivity Analysis of the Conventional BiCMOS Circuit	313	(13)
Delay Time Sensitivity to Key Device Parameters	313	(4)
The Effects of the Load Capacitance on the Circuit Delay Sensitivity	317	(2)
The Effects of the Quality of the BJT on the Circuit Delay Sensitivity	319	(1)
The Effects of Scaling the Technology on the Circuit Delay Sensitivity	320	(2)
HSPICE Simulations and Analysis	322	(4)
Sensitivity Evaluation and Comparison of Low-Voltage, Low-Power BiCMOS Circuits	326	(12)
The Effects of Loading on the Delay and Power Dissipation Sensitivities	331	(5)
The Effects of the Quality of the BJT on the Delay and Power Dissipation Sensitivities	336	(2)
The Effects of Scaling the Technology on the Delay and Power Dissipation Sensitivities	338	(1)
Delay Sensitivity Upper and Lower Bounds: A Worst Case Scenario	338	(1)
Conclusions	339	(2)
References	341	(1)
Appendix	342	(1)
The Authors	343	(2)
Index	345