Mixed Analog-Digital Vlsi Device and Technology

by Tsividis, Yannis

• ISBN13: 9789812381118
• ISBN10: 9812381112
• Format: Hardcover
• Copyright: 2002-11-01
• Publisher: World Scientific Pub Co Inc

Summary

Improve your circuit-design potential with this expert guide to the devices and technology used in mixed analog-digital VLSI chips for such high-volume applications as hard-disk drives, wireless telephones, and consumer electronics. The book provides you with a critical understanding of device models, fabrication technology, and layout as they apply to mixed analog-digital circuits.

You will learn about the many device-modeling requirements for analog work, as well as the pitfalls in models used today for computer simulators such as Spice. Also included is information on fabrication technologies developed specifically for mixed-signal VLSI chips, plus guidance on the layout of mixed analog-digital chips for a high degree of analog-device matching and minimum digital-to-analog interference.

Filled with practical information, this first-of-its-kind book will help you grasp the nuances of mixed-signal VLSI-device models and layout that are crucial to the design of high-performance chips.

Table of Contents

Preface	ix
Introduction: Mixed Analog-Digital Chips	1	(14)
The Role and Place of Modern Mixed Analog-Digital Chips	1	(3)
Advantages of Mixing Analog and Digital Circuits on the Same Chip	4	(1)
Applications of MAD Chips	4	(2)
Obstacles in the Design of MAD Chips	6	(4)
The Aim and Contents of This Book	10	(5)
The MOSFET: Introduction and Qualitative View	15	(32)
Introduction	15	(1)
MOS Transistor Structure	15	(3)
Assumptions about Terminal Voltages, Currents, and Temperature	18	(1)
A Qualitative Description of MOSFET Operation	19	(12)
Effect of VGS: Level of Inversion	19	(4)
Effect of VSB: The Body Effect	23	(1)
Effect of VDS: Drain Current	24	(7)
A Fluid Dynamical Analog	31	(3)
Complete Set of Characteristics	34	(1)
Form of Functional ID-VGS Dependence: Practical Limits for Regions of Inversion	35	(6)
Factors Affecting the Extrapolated Threshold Voltage	41	(2)
Other Factors Affecting the Drain Current	43	(4)
MOSFET DC Modeling	47	(52)
Introduction	47	(1)
DC Model for Weak and for Strong Inversion	48	(15)
The Current Equations	50	(8)
Model Parameters Influenced by the Body Effect	58	(3)
Origin and Validity of the Model	61	(2)
Drain versus Source	63	(1)
Symmetric Models	64	(2)
General Models and Moderate Inversion	66	(4)
Mobility Dependence on Gate and Substrate Bias	70	(3)
Temperature Effects	73	(1)
Small-Dimension Effects	74	(5)
Breakdown	79	(1)
The pMOS Transistor	80	(2)
Device Symbols	82	(1)
Model Accuracy, Parameter Extraction, and Computer Simulation	83	(16)
MOSFET Small-Signal Modeling	99	(48)
Introduction	99	(1)
Small-Signal Conductance Parameters	99	(4)
Expressions for Small-Signal Conductance Parameters in Weak and in Strong Inversion	103	(8)
Gate Transconductance	103	(3)
Body Transconductance	106	(1)
Drain-Source Conductance	107	(3)
Drain-Substrate Conductance	110	(1)
Examples	110	(1)
Small-Signal Parameters in the Presence of Second-Order Effects	111	(1)
Capacitance Parameters	111	(9)
Extrinsic Capacitances	113	(3)
Intrinsic Capacitances in Weak and in Strong Inversion	116	(4)
Intrinsic Cutoff Frequency and Limits of Model Validity	120	(3)
The Transistor at Very High Frequencies	123	(3)
Extrinsic Parasitic Resistances	123	(1)
Intrinsic Nonquasi-static Effects	123	(3)
Noise	126	(8)
Introductory Remarks	126	(3)
MOS Transistor Noise	129	(5)
General Models and Moderate Inversion	134	(4)
Parameter Extraction for Accurate Small-Signal Modeling	138	(2)
Requirements for Good CAD Models	140	(7)
Technology and Available Circuit Components	147	(58)
Introduction	147	(1)
The n-Well CMOS Process	148	(29)
Basic Fabrication Steps and MOS Transistor Structures	148	(10)
Capacitors	158	(5)
Resistors	163	(5)
Inductors	168	(2)
Bipolar Transistors	170	(2)
Interconnects	172	(2)
Electrical Parameters	174	(2)
Input Protection	176	(1)
Latch-up	176	(1)
BiCMOS Processes	177	(14)
Adding High-Performance Bipolar Transistors to CMOS	177	(3)
Bipolar Transistor Models	180	(11)
Other Silicon Processes	191	(2)
Sensors	193	(1)
Trimming	194	(1)
Tolerance and Matching of Electrical Parameters	195	(2)
Chip Size and Yield	197	(2)
The Influence of Pads and Package	199	(6)
Layout	205	(54)
Introduction	205	(1)
Relation of Fabricated Transistors to Layout	206	(2)
Transistor Geometry and Layout	208	(12)
Layout for Device Matching and Precision Parameter Ratios	220	(16)
Capacitor Layout	220	(9)
Resistor Layout	229	(2)
Transistor Layout	231	(3)
A Collection of Rules for Good Matching	234	(2)
Layout for Interference Reduction	236	(12)
Integrated-Circuit Design	248	(11)
Appendix A Additional MOS Transistor Modeling Information	259	(2)
Appendix B A Set of Benchmark Tests for Evaluating Mosfet Models for Analog Design	261	(8)
Appendix C A Sample Spice Input File	269	(6)
Index	275