Mobile 3D Graphics SoC From Algorithm to Chip

by Yoo, Hoi-Jun; Woo, Jeong-Ho; Sohn, Ju-Ho; Nam, Byeong-Gyu

• ISBN13: 9780470823774
• ISBN10: 0470823771
• Edition: 1st
• Format: Hardcover
• Copyright: 2010-03-01
• Publisher: Wiley-IEEE Press

Summary

The first book to explain the principals behind mobile 3D hardware implementation, helping readers understand advanced algorithms, produce low-cost, low-power SoCs, or become familiar with embedded systems As mobile broadcasting and entertainment applications evolve, there is increasing interest in 3D graphics within the field of mobile electronics, particularly for handheld devices. In Mobile 3D Graphics SoC, Yoo provides a comprehensive understanding of the algorithms of mobile 3D graphics and their real chip implementation methods. 3D graphics SoC (System on a Chip) architecture and its interaction with embedded system software are explained with numerous examples. Yoo divides the book into three sections: general methodology of low power SoC, design of low power 3D graphics SoC, and silicon implementation of 3D graphics SoCs and their application to mobile electronics. Full examples are presented at various levels such as system level design and circuit level optimization along with design technology. Yoo incorporates many real chip examples, including many commercial 3D graphics chips, and provides cross-comparisons of various architectures and their performance. Furthermore, while advanced 3D graphics techniques are well understood and supported by industry standards, this is less true in the emerging mobile applications and games market. This book redresses this imbalance, providing an in-depth look at the new OpenGL ES (The Standard for Embedded Accelerated 3D Graphics), and shows what these new embedded systems graphics libraries can provide for 3D graphics and games developers.

Author Biography

Jeong-Ho Woo, Korea Advanced Institute of Science and Technology, Republic of Korea Ju-Ho Sohn, LG Electronics Institute of Technology, Republic of Korea Byeong-Gyu Nam, Samsung Electronics, Republic of Korea Hoi-Jun Yoo, Korea Advanced Institute of Science and Technology, Republic of Korea

Table of Contents

Preface	p. ix
Introduction	p. 1
Mobile 3D Graphics	p. 1
Mobile Devices and Design Challenges	p. 3
Mobile Computing Power	p. 3
Mobile Display Devices	p. 5
Design Challenges	p. 5
Introduction to SoC Design	p. 6
About this Book	p. 7
Application Platform	p. 9
SoC Design Paradigms	p. 9
Platform and Set-based Design	p. 9
Modeling: Memory and Operations	p. 14
System Architecture	p. 18
Reference Machine and API	p. 18
Communication Architecture Design	p. 22
System Analysis	p. 25
Low-power SoC Design	p. 27
CMOS Circuit-level Low-power Design	p. 27
Architecture-level Low-power Design	p. 27
System-level Low-power Design	p. 28
Network-on-Chip based SoC	p. 28
Network-on-Chip Basics	p. 29
NoC Design Considerations	p. 41
Case Studies of Chip Implementation	p. 48
Introduction to 3D Graphics	p. 67
The 3D Graphics Pipeline	p. 68
The Application Stage	p. 68
The Geometry Stage	p. 68
The Rendering Stage	p. 74
Programmable 3D Graphics	p. 78
Programmable Graphics Pipeline	p. 78
Shader Models	p. 81
Mobile 3D Graphics	p. 85
Principles of Mobile 3D Graphics	p. 85
Application Challenges	p. 86
Design Principles	p. 87
Mobile 3D Graphics APIs	p. 91
KAIST MobileGL	p. 91
Khronos OpenGL-ES	p. 93
Microsoft's Direct3D-Mobile	p. 95
Summary and Future Directions	p. 96
Mobile 3D Graphics SoC	p. 99
Low-power Rendering Processor	p. 100
Early Depth Test	p. 101
Logarithmic Datapaths	p. 102
Low-power Texture Unit	p. 104
Tile-based Rendering	p. 106
Texture Compression	p. 107
Texture Filtering and Anti-aliasing	p. 109
Low-power Shader	p. 110
Vertex Cache	p. 110
Low-power Register File	p. 111
Mobile Unified Shader	p. 113
Real Chip Implementations	p. 119
KAIST RAMP Architecture	p. 119
Ramp-IV	p. 120
Ramp-V	p. 123
Ramp-VI	p. 127
Ramp-VII	p. 132
Industry Architecture	p. 139
nVidia Mobile GPU - SC10 and Tegra	p. 139
Sony PSP	p. 143
Imagination Technology MBX/SGX	p. 144
Low-power Rasterizer Design	p. 149
Target System Architecture	p. 149
Summary of Performance and Features	p. 150
Block Diagram of the Rasterizer	p. 150
Instruction Set Architecture (ISA)	p. 151
Detailed Design with Register Transfer Level Code	p. 154
Rasterization Top Block	p. 154
Pipeline Architecture	p. 156
Main Controller Design	p. 156
Rasterization Core Unit	p. 158
The Future of Mobile 3D Graphics	p. 295
Game and Mapping Applications Involving Networking	p. 295
Moves Towards More User-centered Applications	p. 296
Final Remarks	p. 297
Appendix Verilog HDL Design	p. 299
Introduction to Verilog Design	p. 299
Design Level	p. 300
Behavior Level	p. 300
Register Transfer Level	p. 300
Gate Level	p. 300
Design Flow	p. 301
Specification	p. 302
High-level Design	p. 302
Low-level Design	p. 303
RTL Coding	p. 303
Simulation	p. 304
Synthesis	p. 304
Placement and Routing	p. 305
Verilog Syntax	p. 305
Modules	p. 306
Logic Values and Numbers	p. 307
Data Types	p. 308
Operators	p. 309
Assignment	p. 311
Ports and Connections	p. 312
Expressions	p. 312
Instantiation	p. 314
Miscellaneous	p. 316
Example of Four-bit Adder with Zero Detection	p. 318
Synthesis Scripts	p. 320
Glossaries	p. 323
Index	p. 325
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