Mobile 3D Graphics SoC: From Algorithm to Chip

by Hoi-Jun Yoo (Korea Advanced Institute of Science and Technology, Republic of Korea); Jeong-Ho Woo (Korea Advanced Institute of Science and Technology, Republic of Korea); Ju-Ho Sohn (LG Electronics Institute of Technology, Republic of Korea); Byeong-

• ISBN13: 9780470823781
• ISBN10: 047082378X
• Format: eBook
• Copyright: 2010-04-01
• Publisher: Wiley

Summary

The first book to explain the principals behind mobile 3D hardware implementation, helping readers understand advanced algorithms, produce low-cost, low-power SoCs, or become familiar with embedded systems As mobile broadcasting and entertainment applications evolve, there is increasing interest in 3D graphics within the field of mobile electronics, particularly for handheld devices. In Mobile 3D Graphics SoC, Yoo provides a comprehensive understanding of the algorithms of mobile 3D graphics and their real chip implementation methods. 3D graphics SoC (System on a Chip) architecture and its interaction with embedded system software are explained with numerous examples. Yoo divides the book into three sections: general methodology of low power SoC, design of low power 3D graphics SoC, and silicon implementation of 3D graphics SoCs and their application to mobile electronics. Full examples are presented at various levels such as system level design and circuit level optimization along with design technology. Yoo incorporates many real chip examples, including many commercial 3D graphics chips, and provides cross-comparisons of various architectures and their performance. Furthermore, while advanced 3D graphics techniques are well understood and supported by industry standards, this is less true in the emerging mobile applications and games market. This book redresses this imbalance, providing an in-depth look at the new OpenGL ES (The Standard for Embedded Accelerated 3D Graphics), and shows what these new embedded systems graphics libraries can provide for 3D graphics and games developers.

Table of Contents

Preface

Introduction

Mobile 3D Graphics

Mobile Devices and Design Challenges

Mobile Computing Power

Mobile Display Devices

Design Challenges

Introduction to SoC Design

About this Book

Application Platform

SoC Design Paradigms

Platform and Set-based Design

Modeling: Memory and Operations

System Architecture

Reference Machine and API

Communication Architecture Design

System Analysis

Low-power SoC Design

CMOS Circuit-level Low-power Design

Architecture-level Low-power Design

System-level Low-power Design

Network-on-Chip based SoC

Network-on-Chip Basics

NoC Design Considerations

Case Studies of Chip Implementation

Introduction to 3D Graphics

The 3D Graphics Pipeline

The Application Stage

The Geometry Stage

The Rendering Stage

Programmable 3D Graphics

Programmable Graphics Pipeline

Shader Models

Mobile 3D Graphics

Principles of Mobile 3D Graphics

Application Challenges

Design Principles

Mobile 3D Graphics APIs

KAIST MobileGL

Khronos OpenGL-ES

Microsoft's Direct3D-Mobile

Summary and Future Directions

Mobile 3D Graphics SoC

Low-power Rendering Processor

Early Depth Test

Logarithmic Datapaths

Low-power Texture Unit

Tile-based Rendering

Texture Compression

Texture Filtering and Anti-aliasing

Low-power Shader

Vertex Cache

Low-power Register File

Mobile Unified Shader

Real Chip Implementations

KAIST RAMP Architecture

RAMP-IV

RAMP-V

RAMP-VI

RAMP-VII

Industry Architecture

nVidia Mobile GPU - SC10 and Tegra

Sony PSP

Imagination Technology MBX/SGX

Low-power Rasterizer Design

Target System Architecture

Summary of Performance and Features

Block Diagram of the Rasterizer

Instruction Set Architecture (ISA)

Detailed Design with Register Transfer Level Code

Rasterization Top Block

Pipeline Architecture

Main Controller Design

Rasterization Core Unit

The Future of Mobile 3D Graphics

Game and Mapping Applications Involving Networking

Moves Towards More User-centered Applications

Final Remarks

Appendix Verilog HDL Design

Introduction to Verilog Design

Design Level

Behavior Level

Register Transfer Level

Gate Level

Design Flow

Specification

High-level Design

Low-level Design

RTL Coding

Simulation

Synthesis

Placement and Routing

Verilog Syntax

Modules

Logic Values and Numbers

Data Types

Operators

Assignment

Ports and Connections

Expressions

Instantiation

Miscellaneous

Example of Four-bit Adder with Zero Detection

Synthesis Scripts

Glossaries

Index

Table of Contents provided by Publisher. All Rights Reserved.