Model And Design Of Bipolar And Mos Current-mode Logic

by Alioto, Massimo; Palumbo, Gaetano

• ISBN13: 9781402028786
• ISBN10: 1402028784
• Format: Hardcover
• Copyright: 2005-12-15
• Publisher: Kluwer Academic Pub

Summary

The main focus of this book is to provide the reader with a deep understanding of modeling and design strategies of Current-Mode digital circuits, as well as to organize in a coherent manner all the original and powerful authors' results in the domain of Current-Mode digital circuits.Model and Design of Bipolar and MOS Current-Mode Logic includes bipolar Current-Mode digital circuits, which emerged as an approach to realize digital circuits with the highest speed, and CMOS Current-Mode digital circuits, which together with its speed performance has been rediscovered to allow logic gates implementations having the feature of low noise level generation.Model and Design of Bipolar and MOS Current-Mode Logic allows the reader not only to understand the operating principle and the features of bipolar and MOS Current-Mode digital circuits, but also to design optimized digital gates. And, although the material is presented in a formal and theoretical manner, much emphasis is devoted to a design perspective. Moreover, to further link the book's theoretical aspects with practical issues, and to provide the reader with an idea of the real order of magnitude involved assuming actual technologies, numerical examples together with SPICE simulations are included in the book.Model and Design of Bipolar and MOS Current-Mode Logic can be used as a reference to practicing engineers working in this area and as text book to senior undergraduate, graduate and postgraduate students (already familiar with electronic circuits and logic gates) who want to extend their knowledge and cover all aspects of the analysis and design of Current-Mode digital circuits.

Table of Contents

Acknowledgment	xii
Preface	xiii
Device Modeling for Digital Circuits	1	(34)
Gianluca Giustolisi
Rosario Mita
PN Junction	1	(7)
Reverse Bias Condition	4	(2)
Foward Bias Condition	6	(2)
Bipolar-Junction Transistors	8	(7)
Basic Operation	9	(3)
Early Effect or Base Width Modulation	12	(1)
Charge Effects in the Bipolar Transistor	12	(2)
Small Signal Model	14	(1)
Mos Transistors	15	(20)
Basic Operation	16	(2)
Triode or Linear Region	18	(2)
Saturation or Active Region	20	(1)
Body Effect	21	(1)
p-channel Transistors	22	(1)
Charge Effects in Saturation Region	22	(3)
Charge Effects in Triode Region	25	(1)
Charge Effects in Cutoff Region	26	(1)
Small Signal Model	27	(2)
Second Order Effects in MOSFET Modeling	29	(6)
Current-Mode Digital Circuits	35	(50)
The Bipolar Current-Mode Inverter: Basic Principles	35	(2)
The Bipolar Current-Mode Inverter: Input-Output Characteristics and Noise Margin	37	(10)
Differential input/output	37	(5)
Single-ended input/output	42	(3)
Considerations on the non zero input current	45	(1)
Remarks and comparison of differential/single-ended gates	46	(1)
The Buffered Bipolar Current-Mode (ECL) Inverter	47	(2)
The Mos Current-Mode Inverter	49	(12)
Static modeling of the PMOS active load	50	(3)
Input-output characteristics	53	(3)
Evaluation of the noise margin	56	(1)
Validation of the static model	56	(2)
The buffered MOS Current-Mode inverter and remarks	58	(3)
Fundamental Current-Mode Logic Gates	61	(13)
Principle of operation of Current-Mode gates: the series gating concept	61	(3)
Some examples of Current-Mode series gates	64	(5)
Supply voltage limitations in bipolar Current-Mode gates	69	(4)
MOS Current-Mode series gates and supply voltage limitations	73	(1)
Typical Applications of Current-Mode Circuits	74	(11)
Radio Frequency applications	74	(5)
Optic-fiber communications	79	(3)
High-resolution mixed-signal ICs	82	(3)
Design Methodologies for Complex Current-Mode Logic Gates	85	(34)
Basic Concepts on the Design of a Series Gate	85	(10)
Evaluation of function F(X1...X1) implemented by a given topology	87	(3)
Series-gate implementation of an assigned function F(X1...Xn)	90	(5)
Limitations of the general series-gate design approach	95	(1)
A Graphical Reduction Method	95	(8)
Basic concepts on the graphical approach in [CJ89]	95	(4)
A design example	99	(4)
An Analytical Formulation of the Design Strategy in [CJ89]	103	(6)
Analytical interpretation of CPE/NPE	103	(1)
Analytical simplification through CPE/NPE: an example	104	(4)
Circuit implementation of the simplified function after CPE-NPE	108	(1)
A Vem-Based Reduction Method	109	(4)
Input Ordering Versus Design Goal	113	(6)
Modeling of Bipolar Current-Mode Gates	119	(38)
Introduction to Modeling Methodologies	119	(3)
An Efficient Approach for CML Gates	122	(2)
Simple Modeling of the CML Inverter	124	(8)
Accuracy of the CML simple model	127	(5)
Accurate Modeling of the CML Inverter	132	(2)
Accuracy of the CML accurate model	133	(1)
Simple and Accurate Modeling of the ECL Inverter	134	(8)
Validation and improvement of the ECL model	138	(4)
Simple Modeling of Bipolar CML MUX/XOR Gates	142	(6)
Validation of the MUX/XOR model	145	(2)
Extension to the MUX/XOR when upper transistors switch	147	(1)
Accurate Modeling of Bipolar CML MUX/XOR Gates and Extension to ECL Gates	148	(2)
Evaluation of CML/ECL Gates Input Capacitance	150	(1)
Bipolar Current-Mode D Latch	151	(6)
Optimized Design of Bipolar Current-Mode Gates	157	(30)
Introduction to Optimized Methodology in CML Gates	157	(3)
Optimized Design of the CML Inverter	160	(5)
Design with minimum transistor area	160	(2)
Design with non-minimum transistor area	162	(2)
Design examples	164	(1)
Optimized Design of the ECL Inverter	165	(4)
Comparison Between the CML and the ECL Inverter	169	(5)
Optimized Design of Bipolar Current-Mode Mux/Xor and D Latch	174	(10)
Design of MUX/XOR CML gates with minimum transistor area	174	(5)
Design of MUX/XOR CML gates with non-minimum transistor area and examples	179	(2)
Design of the CML D latch	181	(3)
Design examples	184	(1)
Summary and Remarks	184	(3)
Modeling of MOS Current-Mode Gates	187	(32)
Introduction to the Delay Modeling of MOS Current-Mode Gates	187	(1)
Modeling of the Source-Coupled Inverter	188	(10)
Circuit model of the PMOS active load	189	(3)
Delay model of the SCL inverter for a step input	192	(5)
Extension of the delay model to arbitrary input waveforms	197	(1)
Modeling of the Source-Coupled Inverter with Output Buffers	198	(6)
Modeling of the Source-Coupled MUX/XOR Gate	204	(9)
Delay model of the MUX/XOR gate without output buffer	204	(4)
Validation of the model of MUX/XOR gate without output buffer	208	(3)
MUX/XOR with the upper transistor switching	211	(1)
Delay model of the MUX/XOR gate with output buffers	212	(1)
Evaluation of SCL Gates Input Capacitance and Extension to the D Latch	213	(6)
Optimized Design of MOS Current-Mode Gates	219	(46)
Introduction to Optimized Design of SCL Gates	219	(1)
Optimized Design Methodology in SCL Gates without Output Buffers	220	(6)
Power-efficient design	221	(1)
High-speed design	222	(2)
Low-power design	224	(1)
Remarks on the delay dependence on bias current and logic swing	225	(1)
Transistor Sizing to Meet Noise Margin Specification	226	(6)
Design criteria for Vswing and Av to meet a noise margin specification	226	(2)
Transistor sizing versus Iss	228	(2)
Summary and remarks on the transistor sizing versus Iss	230	(2)
Optimized Design of the Source-Coupled Inverter	232	(13)
Delay expression versus bias current and logic swing in region M	233	(3)
Delay expression versus bias current and logic swing in region L and H	236	(2)
Extension of the delay model in the region M to region L and H: a unified expression of delay and remarks	238	(3)
Design criteria and examples	241	(3)
Intuitive understanding of the delay dependence on logic swing and voltage gain in practical design cases	244	(1)
Optimized Design of the Source-Coupled Inverter with Output Buffers	245	(8)
Buffer used as a level shifter	246	(3)
Buffer used to improve speed	249	(4)
Optimized Design of the Source-Coupled MUX/XOR and D Latch	253	(12)
MUX/XOR delay expression versus bias current and logic swing with the lower transistors switching	253	(6)
MUX/XOR delay expression versus bias current and logic swing for input applied to upper transistors	259	(1)
Delay dependence on logic swing	260	(1)
Extension to D latch	261	(4)
Optimized Design of the Source-Coupled MUX/XOR and D Latch with Output Buffers
Comparison of Gates Analyzed and Extension to Arbitrary SCL Logic Gates
Applications and Remarks on Current-Mode Digital Circuits	265	(42)
Ring Oscillators	265	(13)
Bipolar CML ring oscillators	268	(5)
Validation of the oscillation frequency in a CML ring oscillator	273	(4)
Remarks on the oscillation amplitude in a CML ring oscillator	277	(1)
CMOS SCL ring oscillators	278	(1)
Frequency Dividers	278	(6)
Design of the first stage	280	(1)
Design of successive stages	281	(2)
Design considerations and examples	283	(1)
Low-Voltage Bipolar Current-Mode Topologies	284	(14)
Low-voltage CML by means of the triple-tail cell	285	(3)
Analysis of the low-voltage CML D latch static operation	288	(2)
Delay of the low-voltage CML D latch	290	(3)
Comparison of the low-voltage and traditional CML D latch designed for high speed	293	(3)
Comparison of the low-voltage and traditional CML D latch designed for a low power consumption	296	(1)
Summary of results and remarks	297	(1)
Optimized Design Strategies for Cascaded Bipolar Current-Mode Gates	298	(9)
Design of CML non-critical paths with a constraint on the overall bias current	299	(3)
Design of CML critical paths with a constraint on the overall bias current	302	(2)
Design of CML critical paths with a constraint on the overall bias current and equal transistors' emitter area	304	(3)
References	307	(10)
About the Authors	317