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Arvind Raghavan is a Senior Design Engineer for the Intel Corporation.
Nuttapong Srirattana is a Senior Design Engineer at RF Micro Devices.
Joy Laskar holds the Schlumberger Chair in Microelectronics and is the founder and Director of the Georgia Electronic Design Center within the School of Electrical and Computer Engineering at the Georgia Institute of Technology.
Preface | p. ix |
Introduction | p. 1 |
Semiconductor Technology and RF Power Amplifier Design | p. 2 |
Device Modeling | p. 3 |
Power Amplifier IC Design | p. 4 |
Power Amplifier Linearity | p. 5 |
Modulation Schemes | p. 5 |
Circuit Simulation | p. 9 |
Load-Pull Measurements | p. 10 |
References | p. 13 |
Device Modeling for CAD | p. 15 |
Introduction | p. 15 |
Bipolar Junction and Heterojunction Bipolar Transistors | p. 16 |
Bipolar Device Models | p. 18 |
The Ebers-Moll Model | p. 18 |
The Gummel-Poon Model | p. 20 |
The VBIC Model | p. 25 |
MEXTRAM | p. 29 |
HICUM | p. 32 |
MOSFET Device Physics | p. 35 |
MOSFET Device Models | p. 38 |
The Level 1 Model | p. 38 |
The Level 2 and Level 3 Models | p. 40 |
BSIM | p. 40 |
The BSIM2 and HSPICE Level 28 Models | p. 43 |
BSIM3 | p. 44 |
MOS Model 9 and MOS Model 11 | p. 45 |
BSIM4 | p. 45 |
References | p. 46 |
Empirical Modeling of Bipolar Devices | p. 49 |
Introduction | p. 49 |
Modeling the HBT versus the BJT | p. 49 |
Parameter Extraction | p. 50 |
Motivation for an Empirical Bipolar Device Model | p. 51 |
Physics-Based and Empirical Models | p. 53 |
Compatibility between Large- and Small-Signal Models | p. 53 |
Model Construction and Parameter Extraction | p. 54 |
Current Source Model | p. 54 |
Current Source Model Parameter Extraction | p. 56 |
Extraction of Intrinsic Capacitances | p. 58 |
Extraction of Base Resistance | p. 60 |
Parameter Extraction Procedure | p. 61 |
Temperature-Dependent InGaP/GaAs HBT Large-Signal Model | p. 63 |
Empirical Si BJT Large-Signal Model | p. 71 |
Extension of the Empirical Modeling Method to the SiGe HBT | p. 77 |
Summary | p. 83 |
References | p. 83 |
Scalable Modeling of RF Mosfets | p. 87 |
Introduction | p. 87 |
NQS Effects | p. 88 |
Distributed Gate Resistance | p. 89 |
Distributed Substrate Resistance | p. 89 |
Scalable Modified BSIM3v3 Model | p. 91 |
Scalability of MOSFET Model | p. 91 |
Extraction of Small-Signal Model Parameters | p. 94 |
Scalable Substrate Network Modeling | p. 101 |
Modified BSIM3v3 Model | p. 116 |
Summary | p. 120 |
References | p. 120 |
Power Amplifier IC Design | p. 123 |
Introduction | p. 123 |
Power Amplifier Design Methodology | p. 124 |
Classes of Operation | p. 125 |
Performance Metrics | p. 132 |
Thermal Instability and Ballasting | p. 136 |
References | p. 138 |
Power Amplifier Design in Silicon | p. 141 |
Introduction | p. 141 |
A 2.4-GHz High-Efficiency SiGe HBT Power Amplifier | p. 142 |
Circuit Design Considerations | p. 143 |
Analysis of Ballasting for SiGe HBT Power Amplifiers | p. 146 |
Harmonic Suppression Filter and Output Match Network | p. 148 |
Performance of the Power Amplifier Module | p. 150 |
RF Power Amplifier Design Using Device Periphery Adjustment | p. 153 |
Analysis of the Device Periphery Adjustment Technique | p. 155 |
1.9-GHz CMOS Power Amplifier | p. 157 |
1.9-GHz CDMA/PCS SiGe HBT Power Amplifier | p. 162 |
Nonlinear Term Cancellation for Linearity Improvement | p. 166 |
References | p. 169 |
Efficiency Enhancement of RF Power Amplifiers | p. 173 |
Introduction | p. 173 |
Efficiency Enhancement Techniques | p. 174 |
Envelope Elimination and Restoration | p. 174 |
Bias Adaptation | p. 175 |
The Doherty Amplifier Technique | p. 175 |
Chireix's Outphasing Amplifier Technique | p. 176 |
The Classical Doherty Amplifier | p. 179 |
The Multistage Doherty Amplifier | p. 181 |
Principle of Operation | p. 181 |
Analysis of Efficiency | p. 186 |
Practical Considerations | p. 188 |
Measurement Results | p. 190 |
References | p. 198 |
Index | p. 199 |
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