Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL

by Ciletti, Michael D.

• ISBN13: 9780139773983
• ISBN10: 0139773983
• Edition: 1st
• Format: Paperback
• Copyright: 1999-03-08
• Publisher: Pearson

Summary

Verilogaims to introduce new users to the language of Verilog with instruction on how to write hardware descriptions in Verilog in a style that can be synthesized by readily available synthesis tools.Offers clear exposition of the Verilog hardware description language. This book is written in a style that allows the user who has no previous background with hardware description languages (HDLs) to become skillful with the language. Features treatment of synthesis-friendly descriptive styles.An excellent book for self-study, reference, seminars, and workshops on the subject.

Table of Contents

PREFACE	xix
Chapter 1 INTRODUCTION TO ELECTRONIC DESIGN AUTOMATION	1	(21)
1.1 ELECTRONIC DESIGN AUTOMATION	1	(12)
1.1.1 Design Flow	2	(4)
1.1.2 Design Entry	6	(1)
1.1.3 Schematic-Based Design Entry	6	(2)
1.1.4 Design Entry Based on a Hardware Description Language	8	(4)
1.1.5 Hints for Model Development	12	(1)
1.2 A BRIEF HISTORY OF HDLs	13	(1)
1.3 THE ROLE AND REQUIREMENTS OF HARDWARE DESCRIPTION LANGUAGES IN EDA	14	(2)
1.4 BENEFITS OF USING HDLs IN EDA	16	(2)
1.5 SUMMARY	18	(1)
REFERENCES	19	(1)
PROBLEMS	20	(2)
Chapter 2 HARDWARE MODELING WITH THE VERILOG HDL	22	(41)
2.1 HARDWARE ENCAPSULATION: THE VERILOG MODULE	23	(5)
2.1.1 Module Ports	26	(1)
2.1.2 Module Implementation	26	(2)
2.2 HARDWARE MODELING: VERILOG PRIMITIVES	28	(4)
2.3 DESCRIPTIVE STYLES	32	(5)
2.3.1 Explicit Structural Description	33	(1)
2.3.2 Implicit Structural Description--Continuous Assignments	34	(2)
2.3.3 Multiple Instantiations and Assignments	36	(1)
2.4 STRUCTURAL CONNECTIONS	37	(3)
2.4.1 Module Port Connections	37	(2)
2.4.2 Primitive Terminal Connections	39	(1)
2.4.3 Empty Port Connections	39	(1)
2.5 BEHAVIORAL DESCRIPTIONS IN VERILOG	40	(4)
2.5.1 RTL/Data Flow Descriptions	40	(1)
2.5.2 Algorithm-Based Descriptions	41	(3)
2.6 HIERARCHICAL DESCRIPTIONS OF HARDWARE	44	(1)
2.7 STRUCTURED (TOP-DOWN) DESIGN METHODOLOGY	45	(3)
2.8 ARRAYS OF INSTANCES	48	(3)
2.9 USING VERILOG FOR SYNTHESIS	51	(5)
2.10 LANGUAGE CONVENTIONS	56	(1)
2.11 REPRESENTATION OF NUMBERS	56	(2)
2.12 SUMMARY	58	(1)
REFERENCES	58	(1)
PROBLEMS	58	(5)
Chapter 3 EVENT-DRIVEN SIMULATION AND TESTBENCHES	63	(18)
3.1 SIMULATION WITH VERILOG	63	(7)
3.1.1 Event-Driven Simulation	64	(1)
3.1.2 Simulation Data Structures	65	(1)
3.1.3 Effect of Propagation Delay	66	(1)
3.1.4 Inertial Delay and Event De-scheduling	67	(3)
3.2 DESIGN UNIT TESTBENCH	70	(8)
3.3 SUMMARY	78	(1)
PROBLEMS	78	(3)
Chapter 4 LOGIC SYSTEM, DATA TYPES, AND OPERATORS FOR MODELING IN VERILOG HDL	81	(37)
4.1 VARIABLES	81	(1)
4.2 LOGIC VALUE SET	82	(1)
4.3 DATA TYPES	83	(15)
4.3.1 Net Data Types	84	(4)
4.3.2 Initial Value of a Net	88	(1)
4.3.3 Wired Logic	89	(1)
4.3.4 Undeclared Nets--Default Net Type	90	(1)
4.3.5 Register Data Types	91	(1)
4.3.6 Initial Value of a Register Variable	92	(1)
4.3.7 Undeclared Register Variables	92	(1)
4.3.8 Addressing Register Variables	92	(1)
4.3.9 Passing Variables Through Ports	92	(1)
4.3.10 Two-Dimensional Arrays (Memories)	93	(2)
4.3.11 Data Type: integer	95	(1)
4.3.12 Data Type: real	95	(1)
4.3.13 Data Type: time	95	(1)
4.3.14 Data Type: realtime	96	(1)
4.3.15 Scope of a Variable	96	(1)
4.3.16 Variable References and Hierarchical De-referencing	96	(2)
4.4 STRINGS	98	(1)
4.5 CONSTANTS	98	(2)
4.5.1 Direct Substitution of Parameters	99	(1)
4.5.2 Indirect Substitution of Parameters	100	(1)
4.6 OPERATORS	100	(9)
4.6.1 Arithmetic Operators	101	(1)
4.6.2 Bitwise Operators	102	(2)
4.6.3 Reduction Operators	104	(1)
4.6.4 Logical Operators	104	(1)
4.6.5 Relational Operators	105	(1)
4.6.6 Shift Operators	106	(1)
4.6.7 Conditional Operator	107	(1)
4.6.8 Concatenation Operator	108	(1)
4.7 EXPRESSIONS AND OPERANDS	109	(1)
4.8 OPERATOR PRECEDENCE	109	(1)
4.9 SUMMARY	110	(1)
REFERENCES	111	(1)
PROBLEMS	111	(7)
Chapter 5 USER-DEFINED PRIMITIVES	118	(13)
5.1 USER-DEFINED PRIMITIVES: COMBINATIONAL BEHAVIOR	118	(3)
5.2 USER-DEFINED PRIMITIVES--SEQUENTIAL BEHAVIOR	121	(6)
5.2.1 Level-Sensitive Behavior	121	(2)
5.2.2 Edge-Sensitive Behavior	123	(1)
5.2.3 Mixed Behavior (Level-and Edge-Sensitive)	124	(2)
5.2.4 Additional UDP Notation	126	(1)
5.2.5 Treatment of Multiple Events.	127	(1)
5.3 INITIALIZATION OF SEQUENTIAL PRIMITIVES	127	(3)
5.4 SUMMARY	130	(1)
PROBLEMS	130	(1)
Chapter 6 VERILOG MODELS OF PROPAGATION DELAY	131	(28)
6.1 BUILT-IN CONSTRUCTS FOR DELAY	131	(1)
6.2 SIGNAL TRANSITIONS	132	(1)
6.3 VERILOG MODELS FOR GATE PROPAGATION DELAY (Inertial Delay)	133	(3)
6.4 TIME SCALES FOR SIMULATION	136	(4)
6.5 VERILOG MODELS FOR NET DELAY (Transport Delay)	140	(3)
6.6 MODULE PATHS AND DELAYS	143	(9)
6.6.1 Specify Blocks	144	(3)
6.6.2 Simple Module Paths	147	(1)
6.6.3 Edge-Sensitive Paths	148	(1)
6.6.4 State-Dependent Paths	149	(1)
6.6.5 Path Polarity	150	(1)
6.6.6 Specify Block Parameters	150	(2)
6.7 PATH DELAYS AND SIMULATION	152	(1)
6.8 INERTIAL DELAY EFFECTS AND PULSE REJECTION	152	(2)
6.9 SUMMARY	154	(1)
REFERENCE	154	(1)
PROBLEMS	155	(4)
Chapter 7 BEHAVIORAL DESCRIPTIONS IN VERILOG HDL	159	(122)
7.1 VERILOG BEHAVIORS	162	(1)
7.2 BEHAVIORAL STATEMENTS	163	(3)
7.3 PROCEDURAL ASSIGNMENT	166	(1)
7.4 PROCEDURAL CONTINUOUS ASSIGNMENT	167	(5)
7.4.1 assign...deassign Procedural Continuous Assignment	168	(3)
7.4.2 force...release Procedural Continuous Assignment	171	(1)
7.5 PROCEDURAL TIMING CONTROLS AND SYNCHRONIZATION	172	(12)
7.5.1 Delay Control Operator (#)	173	(2)
7.5.2 Event Control Operator (@)	175	(3)
7.5.3 Event or	178	(2)
7.5.4 Named Events	180	(3)
7.5.5 The wait Construct	183	(1)
7.6 INTRA-ASSIGNMENT DELAY--BLOCKED ASSIGNMENTS	184	(1)
7.7 NON-BLOCKING ASSIGNMENT	185	(2)
7.8 INTRA-ASSIGNMENT DELAY: NON-BLOCKING ASSIGNMENT	187	(6)
7.9 SIMULATION OF SIMULTANEOUS PROCEDURAL ASSIGNMENTS	193	(3)
7.10 REPEATED INTRA-ASSIGNMENT DELAY	196	(2)
7.11 INDETERMINATE ASSIGNMENTS AND AMBIGUITY	198	(4)
7.12 CONSTRUCTS FOR ACTIVITY FLOW CONTROL	202	(21)
7.12.1 Activity Flow Control: Conditional Operator (? ... :)	203	(1)
7.12.2 Activity Flow Control: The case Statement (case, casex, casez)	203	(3)
7.12.3 Activity Flow Control: Conditional Statement (if...else)	206	(2)
7.12.4 Activity Flow Control: Loops	208	(1)
7.12.4.1 The repeat Loop	208	(1)
7.12.4.2 The for Loop	209	(7)
7.12.4.3 The while Loop	216	(2)
7.12.4.4 The forever Loop	218	(1)
7.12.4.5 Comparison of Loops	219	(1)
7.12.4.6 Comparison of "always" and "forever"	219	(1)
7.12.5 The disable Statement	219	(1)
7.12.6 Parallel Activity Flow: The fork...join Statement	220	(2)
7.12.7 Race Conditions and the fork...join Statement	222	(1)
7.13 TASKS AND FUNCTIONS	223	(6)
7.13.1 Tasks	223	(2)
7.13.2 Rules for Tasks	225	(1)
7.13.3 Functions	225	(4)
7.14 SUMMARY OF DELAY CONSTRUCTS IN VERILOG	229	(1)
7.15 SYSTEM TASKS FOR TIMING CHECKS	230	(7)
7.15.1 Setup and Hold Conditions ($setup, $hold, $setuphold)	231	(2)
7.15.2 Signal Period ($period)	233	(1)
7.15.3 Minimum Pulse Width ($width)	234	(1)
7.15.4 Signal Skew ($skew)	234	(1)
7.15.5 Recovery Time ($recovery)	235	(1)
7.15.6 No Signal Change ($nochange)	235	(1)
7.15.7 Edge Semantics for Timing Checks	235	(1)
7.15.8 Conditioned Events for Timing Checks	236	(1)
7.16 VARIABLE SCOPE REVISITED	237	(1)
7.17 MODULE CONTENTS	237	(1)
7.18 BEHAVIOURAL MODELS OF FINITE STATE MACHINES	238	(25)
7.18.1 Explicit Finite State Machines	239	(16)
7.18.2 Implicit Finite State Machines	255	(5)
7.18.3 Handshaking	260	(3)
7.19 SUMMARY	263	(1)
REFERENCES	264	(1)
PROBLEMS	264	(17)
Chapter 8 SYNTHESIS OF COMBINATIONAL LOGIC	281	(64)
8.1 HDL-BASED SYNTHESIS	281	(12)
8.1.1 Logic Synthesis	284	(8)
8.1.2 Register Transfer Level (RTL) Synthesis	292	(1)
8.1.3 Finite State Machine Synthesis	292	(1)
8.1.4 Behavioral Synthesis	292	(1)
8.2 TECHNOLOGY-INDEPENDENT DESIGN	293	(2)
8.3 BENEFITS OF SYNTHESIS	295	(1)
8.4 SYNTHESIS METHODOLOGY	296	(1)
8.5 VENDOR SUPPORT	296	(2)
8.5.1 Commonly-Supported Verilog Constructs	297	(1)
8.5.2 Unsupported and Ignored Constructs	297	(1)
8.6 STYLES FOR SYNTHESIS OF COMBINATIONAL LOGIC	298	(32)
8.6.1 Combinational Synthesis from a Netlist of Primitives	299	(4)
8.6.2 Combinational Synthesis from UDPs	303	(1)
8.6.3 Combinational Synthesis from Continuous Assignments	304	(1)
8.6.4 Combinational Synthesis from a Cyclic Behavior	305	(4)
8.6.5 Combinational Synthesis from a Function or Task	309	(1)
8.6.6 Combinational Synthesis from Interconnected Modules	310	(1)
8.6.7 Constructs to Avoid in Combinational Synthesis	310	(1)
8.6.8 Simulation Efficiency and Procedural Continuous Assignments	311	(1)
8.6.9 Synthesis of Control Logic for Multiplexed Datapaths	312	(5)
8.6.10 Unexpected and Unwanted Latches	317	(6)
8.6.11 Synthesis of Priority Structures	323	(1)
8.6.12 Treatment of Default Conditions	324	(6)
8.7 TECHNOLOGY MAPPING AND SHARED RESOURCES	330	(3)
8.8 THREE-STATE BUFFERS	333	(3)
8.8.1 Buses	334	(1)
8.8.2 Bi-directional Bus Drivers	334	(1)
8.8.3 Bus Loading	335	(1)
8.9 THREE-STATE OUTPUTS AND DON'T-CARES	336	(2)
8.10 SUMMARY	338	(1)
REFERENCES	338	(1)
PROBLEMS	339	(6)
Chapter 9 SYNTHESIS OF SEQUENTIAL LOGIC	345	(80)
9.1 SYNTHESIS OF SEQUENTIAL UDPs	345	(3)
9.2 SYNTHESIS OF LATCHES	348	(6)
9.3 SYNTHESIS OF EDGE-TRIGGERED FLIP-FLOPS	354	(4)
9.4 REGISTERED COMBINATIONAL LOGIC	358	(3)
9.5 SHIFT REGISTERS AND COUNTERS	361	(17)
9.6 SYNTHESIS OF FINITE STATE MACHINES	378	(34)
9.6.1 Modeling the Combinational Logic of an FSM	378	(7)
9.6.2 Synthesis of Explicit State Machines	385	(1)
9.6.3 Synthesis of Implicit Finite State Machines	386	(6)
9.6.4 Pitfalls in Modeling State Machines	392	(12)
9.6.5 Some Rules for Implicit FSMs	404	(5)
9.6.6 Comparison of Explicit and Implicit FSMs	409	(1)
9.6.7 State Encoding and One-Hots	409	(3)
9.7 RESETS	412	(2)
9.8 SYNTHESIS OF GATED CLOCKS	414	(1)
9.9 DESIGN PARTITIONS AND HIERARCHICAL STRUCTURES	415	(2)
9.10 SUMMARY	417	(1)
9.10 PROBLEMS	417	(8)
Chapter 10 SYNTHESIS OF LANGUAGE CONSTRUCTS	425	(70)
10.1 SYNTHESIS OF NETS	425	(1)
10.2 SYNTHESIS OF REGISTER VARIABLES	426	(3)
10.2.1 Synthesis of Integers	427	(1)
10.2.2 Synthesis of real, time and realtime Variables	427	(1)
10.2.3 Synthesis of Memories(Arrays)	427	(2)
10.2.4 Synthesis of Strings	429	(1)
10.3 RESTRICTIONS ON SYNTHESIS OF "X" AND "Z"	429	(1)
10.4 SYNTHESIS OF EXPRESSIONS AND OPERATORS	429	(17)
10.4.1 Synthesis of Arithmetic Operators	429	(2)
10.4.2 Synthesis of Non-Arithmetic Operators	431	(1)
10.4.3 Synthesis of Shift Operators	431	(3)
10.4.4 Synthesis of Relational and Identity Operators	434	(3)
10.4.5 Synthesis of Reduction, Bitwise, and Logical Operators	437	(7)
10.4.6 Conditional Operator	444	(1)
10.4.7 Synthesis of the Concatenation Operator	445	(1)
10.4.8 Grouping of Operators	445	(1)
10.5 SYNTHESIS OF ASSIGNMENTS	446	(11)
10.5.1 Synthesis of Continuous Assignments	446	(1)
10.5.2 Synthesis of Procedural Assignments	446	(1)
10.5.3 Expression Substitution in Procedural Assignments	447	(3)
10.5.4 Synthesis of Non-Blocking Assignments	450	(5)
10.5.5 More Pitfalls in Modeling State Machines	455	(2)
10.6 SYNTHESIS OF case AND CONDITIONAL (if...) STATEMENTS	457	(4)
10.7 SYNTHESIS OF RESETS	461	(2)
10.8 TIMING CONTROLS IN SYNTHESIS	463	(4)
10.8.1 Delay Controls	463	(1)
10.8.2 Event Controls	463	(1)
10.8.3 Multiple Event Controls	464	(1)
10.8.4 Synthesis of the wait Statement	465	(1)
10.8.5 Synthesis of Named Events	465	(2)
10.9 SYNTHESIS OF MULTI-CYCLE OPERATIONS	467	(2)
10.10 SYNTHESIS OF LOOPS	469	(16)
10.10.1 Static Loops Without Internal Timing Controls	470	(5)
10.10.2 Static Loops With Internal Timing Controls	475	(1)
10.10.3 Non-Static Loops Without Internal Timing Controls	476	(2)
10.10.4 Non-Static Loops With Internal Timing Controls	478	(4)
10.10.5 State Machine Replacements for Loops	482	(3)
10.11 SYNTHESIS OF fork... join BLOCKS	485	(1)
10.12 SYNTHESIS OF THE disable STATEMENT	485	(2)
10.13 SYNTHESIS OF USER-DEFINED TASKS	487	(1)
10.14 SYNTHESIS OF USER-DEFINED FUNCTIONS	488	(1)
10.15 SYNTHESIS OF SPECIFY BLOCKS	489	(1)
10.16 SYNTHESIS OF COMPILER DIRECTIVES	489	(1)
10.17 SUMMARY	489	(2)
REFERENCES	491	(1)
PROBLEMS	491	(4)
Chapter 11 SWITCH-LEVEL MODELS IN VERILOG	495	(39)
11.1 MOS TRANSISTOR TECHNOLOGY	495	(3)
11.2 SWITCH-LEVEL MODELS OF MOS TRANSISTORS	498	(1)
11.3 SWITCH-LEVEL MODELS OF STATIC CMOS CIRCUITS	498	(2)
11.4 ALTERNATIVE LOADS AND PULL GATES	500	(1)
11.5 CMOS TRANSMISSION GATES	501	(7)
11.6 BI-DIRECTIONAL GATES (SWITCHES)	508	(1)
11.7 SIGNAL STRENGTHS	509	(2)
11.7.1 Strength of a "Driven" Net	511	(1)
11.7.2 Supply Nets	512	(1)
11.7.3 Charge Storage Nets	512	(1)
11.8 AMBIGUOUS SIGNALS	512	(1)
11.9 STRENGTH REDUCTION BY PRIMITIVES	513	(3)
11.9.1 Transistor Switch and Bi-Directional Switches	513	(1)
11.9.2 Resistive MOS Devices	514	(2)
11.10 COMBINATION AND RESOLUTION OF SIGNAL STRENGTHS	516	(8)
11.10.1 Signal Contention: Known Strength and Known Value	516	(6)
11.10.2 Combination of Ambiguous Strength and Known Value	522	(2)
11.11 SIGNAL STRENGTHS AND WIRED LOGIC	524	(1)
11.12 SUMMARY	525	(1)
REFERENCES	525	(1)
PROBLEMS	526	(8)
Chapter 12 DESIGN EXAMPLES IN VERILOG	534	(76)
12.1 FIFO--BUFFERS FOR DATA ACQUISITION	534	(14)
12.2 FIFO APPLICATION: TEMPERATURE MONITOR SYSTEM	548	(19)
12.3 UART	567	(27)
12.3.1 UART--Transmitter	570	(10)
12.3.2 UART--Receiver	580	(14)
12.4 BIT-SLICE MICROCONTROLLER	594	(14)
12.5 SUMMARY	608	(1)
REFERENCES	608	(1)
PROBLEMS	608	(2)
Chapter 13 RAPID PROTOTYPING WITH XILINX FPGAs	610	(37)
13.1 INTRODUCTION TO FPGAs	610	(2)
13.2 ROLE OF FPGAs IN THE ASIC MARKET	612	(2)
13.3 FPGA TECHNOLOGIES	614	(6)
13.4 THE XILINX XC3000 FPGA FAMILY	620	(7)
13.4.1 The XC3000 Configurable Logic Block (CLB)	620	(2)
13.4.2 XC3000 Interconnect Resources	622	(1)
13.4.3 XC3000 Switch Box Functional Configuration and Connectivity	623	(1)
13.4.4 XC3000 I/O Block (IOB)	624	(2)
13.4.5 XC3000 Performance	626	(1)
13.5 THE XC4000 FPGA FAMILY	627	(6)
13.5.1 XC4000 Configurable Logic Block (CLB)	627	(1)
13.5.2 XC4000 Interconnect Resources	628	(3)
13.5.3 XC4000 I/O Block (IOB)	631	(2)
13.5.4 Enhancements in the XC4000E and XC4000X Series	633	(1)
13.6 RAPID PROTOTYPING WITH VERILOG AND FPGAs	633	(1)
13.7 DESIGN EXERCISES	634	(7)
13.7.1 Microcontroller	635	(1)
13.7.2 Electronic Roulette Wheel	635	(6)
13.7.3 Electronic Dice Game	641	(1)
13.8 SUMMARY	641	(1)
REFERENCES	641	(1)
PROBLEMS	642	(5)
Appendix A PREDEFINED PRIMITIVES	647	(12)
A.1 MULTI-INPUT COMBINATIONAL LOGIC GATES	648	(2)
A.2 MULTI-OUTPUT COMBINATIONAL GATES	650	(1)
A.3 THREE-STATE GATES	650	(2)
A.4 MOS TRANSISTOR SWITCHES	652	(4)
A.5 MOS PULL-UP/PULL-DOWN GATES	656	(1)
A.6 MOS BI-DIRECTIONAL SWITCHES	657	(2)
Appendix B VERILOG KEYWORDS	659	(1)
Appendix C VERILOG OPERATORS AND PRECENDENCE	660	(2)
Appendix D BACKUS-NAUR (BNF) FORMAL SYNTAX NOTATION	662	(1)
Appendix E SYSTEM TASKS AND FUNCTIONS	663	(26)
E.1 DISPLAY TASKS	665	(5)
E.2 FILE I/O TASKS	670	(3)
E.3 TIME-SCALE TASKS	673	(1)
E.4 SIMULATION CONTROL TASKS	674	(1)
E.5 PLA MODELING TASKS	675	(3)
E.6 STOCHASTIC ANALYSIS TASKS	678	(2)
E.7 SIMULATION-TIME TASKS	680	(1)
E.8 CONVERSION TASKS	681	(1)
E.9 TIMING-CHECK TASKS	681	(1)
E.10 PROBABILITY DISTRIBUTIONS	682	(2)
E.11 VALUE-CHANGE DUMP (VCD) FILE TASKS	684	(1)
E.12 ADDITIONAL (NONSTANDARD) TASKS	684	(5)
Appendix F VERILOG LANGUAGE FORMAL SYNTAX	689	(13)
F.1 Source Text	689	(1)
F.2 Declarations	690	(2)
F.3 Primitive Instances	692	(1)
F.4 Module Instantiation	693	(1)
F.5 UDP Declaration and Instantiation	693	(1)
F.6 Behavioral Statements	694	(2)
F.7 Specify Section	696	(3)
F.8 Expressions	699	(2)
F.9 General	701	(1)
Appendix G PROGRAMMING LANGUAGE INTERFACE (PLI)	702	(2)
Appendix H COMPILER DIRECTIVES	704	(4)
H.1 `celldefine and `endcelldefine	704	(1)
H.2 `defaultnettype	704	(1)
H.3 `define and `undef	705	(1)
H.4 `ifdef, `else, `endif	705	(1)
H.5 `include	706	(1)
H.6 `resetall	706	(1)
H.7 `timescale	706	(1)
H.8 `nounconnected_drive and `unconnected_drive	707	(1)
Appendix I FLIP-FLOP AND LATCH TYPES	708	(2)
INDEX	710	(15)
XILINIX STUDENT EDITION	725