Nano-Cmos Circuit and Physical Design

by Wong, Ban; Mittal, Anurag; Cao, Yu; Starr, Greg W.

• ISBN13: 9780471466109
• ISBN10: 0471466107
• Edition: 1st
• Format: Hardcover
• Copyright: 2004-11-29
• Publisher: Wiley-IEEE Press

Summary

Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation.

Author Biography

BAN P. WONG, IENG MIEE, served for five years as a member of the technical program committee of IEEE International Solid-State Circuits Conference and as session chair, cochair, and organizer of a panel session. He has three issued patents. He has led circuit design teams in developing methodology and implementation of high-performance and low-power microprocessors. He is currently Senior Engineering Manager for NVIDIA Corporation. <p> ANURAG MITTAL received his PhD in applied physics from Yale University. He has codeveloped novel embedded NVM microcontroller and microprocessor solutions including the world&#8217;s first truly CMOS-compatible Flash technology. He is Senior Staff Engineer for Virage Logic, Inc. <p> YU CAO received his PhD in electrical engineering from University of California, Berkeley. He is a postdoctoral researcher in the Berkeley Wireless Research Center. He received the 2000 Beatrice Winner Award at the IEEE International Solid-State Circuits Conference. <p> GREG STARR received his PhD in electrical engineering from Arizona State University. Currently, he is a Senior Design Manager at Xilinx Corporation.

Table of Contents

Foreword	xiii
Preface	xv
Nano-CMOS Scaling Problems and Implications	1	(23)
Design Methodology in the Nano-CMOS Era	1	(2)
Innovations Needed to Continue Performance Scaling	3	(3)
Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography	6	(9)
Back-End-of-Line Challenges (Metallization)	6	(6)
Front-End-of-Line Challenges (Transistors)	12	(3)
Process Control and Reliability	15	(1)
Lithographic Issues and Mask Data Explosion	16	(1)
New Breed of Circuit and Physical Design Engineers	17	(1)
Modeling Challenges	17	(2)
Need for Design Methodology Changes	19	(2)
Summary	21	(3)
References	21	(3)
PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS
CMOS Device and Process Technology	24	(49)
Equipment Requirements for Front-End Processing	24	(17)
Technical Background	24	(2)
Gate Dielectric Scaling	26	(7)
Strain Engineering	33	(1)
Rapid Thermal Processing Technology	34	(7)
Front-End-Device Problems in CMOS Scaling	41	(17)
CMOS Scaling Challenges	41	(2)
Quantum Effects Model	43	(2)
Polysilicon Gate Depletion Effects	45	(3)
Metal Gate Electrodes	48	(1)
Direct-Tunneling Gate Leakage	49	(3)
Parasitic Capacitance	52	(4)
Reliability Concerns	56	(2)
Back-End-of-Line Technology	58	(15)
Interconnect Scaling	59	(2)
Copper Wire Technology	61	(3)
Low-k Dielectric Challenges	64	(1)
Future Global Interconnect Technology	65	(1)
References	66	(7)
Theory and Practicalities of Subwavelength Optical Lithography	73	(61)
Introduction and Simple Imaging Theory	73	(3)
Challenges for the 100-nm Node	76	(15)
κ-Factor for the 100-nm Node	77	(1)
Significant Process Variations	78	(4)
Impact of Low-κ Imaging on Process Sensitivities	82	(1)
Low-κ Imaging and Impact on Depth of Focus	83	(1)
Low-κ Imaging and Exposure Tolerance	84	(1)
Low-κ Imaging and Impact on Mask Error Enhancement Factor	84	(2)
Low-κ Imaging and Sensitivity to Aberrations	86	(1)
Low-κ Imaging and CD Variation as a Function of Pitch	86	(3)
Low-κ Imaging and Corner Rounding Radius	89	(2)
Resolution Enhancement Techniques: Physics	91	(16)
Specialized Illumination Patterns	92	(2)
Optical Proximity Corrections	94	(7)
Subresolution Assist Features	101	(2)
Alternating Phase-Shift Masks	103	(4)
Physical Design Style Impact on RET and OPC Complexity	107	(14)
Specialized Illumination Conditions	108	(3)
Two-Dimensional Layouts	111	(3)
Alternating Phase-Shift Masks	114	(4)
Mask Costs	118	(3)
The Road Ahead: Future Lithographic Technologies	121	(13)
The Evolutionary Path: 157-nm Lithography	121	(1)
Still Evolutionary: Immersion Lithography	122	(2)
Quantum Leap: EUV Lithography	124	(2)
Particle Beam Lithography	126	(1)
Direct-Write Electron Beam Tools	126	(4)
References	130	(4)
PART II PROCESS SCALING IMPACT ON DESIGN
Mixed-Signal Circuit Design	134	(38)
Introduction	134	(1)
Design Considerations	134	(1)
Device Modeling	135	(7)
Passive Components	142	(4)
Design Methodology	146	(4)
Benchmark Circuits	146	(1)
Design Using Thin Oxide Devices	146	(2)
Design Using Thick Oxide Devices	148	(2)
Low-Voltage Techniques	150	(5)
Current Mirrors	150	(2)
Input Stages	152	(1)
Output Stages	153	(1)
Bandgap References	154	(1)
Design Procedures	155	(2)
Electrostatic Discharge Protection	157	(2)
Multiple-Supply Concerns	157	(2)
Noise Isolation	159	(3)
Guard Ring Structures	159	(2)
Isolated NMOS Devices	161	(1)
Epitaxial Material versus Bulk Silicon	161	(1)
Decoupling	162	(4)
Power Busing	166	(1)
Integration Problems	167	(1)
Corner Regions	167	(1)
Neighboring Circuitry	167	(1)
Summary	168	(4)
References	168	(4)
Electrostatic Discharge Protection Design	172	(48)
Introduction	172	(1)
ESD Standards and Models	173	(1)
ESD Protection Design	173	(5)
ESD Protection Scheme	173	(2)
Turn-on Uniformity of ESD Protection Devices	175	(2)
ESD Implantation and Silicide Blocking	177	(1)
ESD Protection Guidelines	178	(1)
Low-C ESD Protection Design for High-Speed I/O	178	(12)
ESD Protection for High-Speed I/O or Analog Pins	178	(2)
Low-C ESD Protection Design	180	(3)
Input Capacitance Calculations	183	(2)
ESD Robustness	185	(1)
Turn-on Verification	186	(4)
ESD Protection Design for Mixed-Voltage I/O	190	(10)
Mixed-Voltage I/O Interfaces	190	(1)
ESD Concerns for Mixed-Voltage I/O Interfaces	191	(1)
ESD Protection Device for a Mixed-Voltage I/O Interface	192	(3)
ESD Protection Circuit Design for a Mixed-Voltage I/O Interface	195	(3)
ESD Robustness	198	(1)
Turn-on Verification	199	(1)
SCR Devices for ESD Protection	200	(12)
Turn-on Mechanism of SCR Devices	201	(1)
SCR-Based Devices for CMOS On-Chip ESD Protection	202	(8)
SCR Latch-up Engineering	210	(2)
Summary	212	(8)
References	213	(7)
Input/Output Design	220	(21)
Introduction	220	(1)
I/O Standards	221	(1)
Signal Transfer	222	(5)
Single-Ended Buffers	223	(1)
Differential Buffers	223	(4)
ESD Protection	227	(1)
I/O Switching Noise	228	(4)
Termination	232	(2)
Impedance Matching	234	(1)
Preemphasis	235	(2)
Equalization	237	(1)
Conclusion	238	(3)
References	239	(2)
Dram	241	(14)
Introduction	241	(1)
Dram Basics	241	(4)
Scaling the Capacitor	245	(2)
Scaling the Array Transistor	247	(2)
Scaling the Sense Amplifier	249	(4)
Summary	253	(2)
References	253	(2)
Signal Integrity Problems in On-Chip Interconnects	255	(43)
Introduction	255	(4)
Interconnect Figures of Merit	258	(1)
Interconnect Parasitics Extraction	259	(12)
Circuit Representation of Interconnects	260	(3)
RC Extraction	263	(4)
Inductance Extraction	267	(4)
Signal Integrity Analysis	271	(12)
Interconnect Driver Models	272	(2)
RC Interconnect Analysis	274	(3)
RLC Interconnect Analysis	277	(4)
Noise-Aware Timing Analysis	281	(2)
Design Solutions for Signal Integrity	283	(10)
Physical Design Techniques	284	(4)
Circuit Techniques	288	(5)
Summary	293	(5)
References	294	(4)
Ultralow Power Circuit Design	298	(33)
Introduction	298	(2)
Design-Time Low-Power Techniques	300	(11)
System- and Architecture-Level Design-Time Techniques	300	(1)
Circuit-Level Design-Time Techniques	300	(5)
Memory Techniques at Design Time	305	(6)
Run-Time Low-Power Techniques	311	(9)
System- and Architecture-Level Run-Time Techniques	311	(2)
Circuit-Level Run-Time Techniques	313	(3)
Memory Techniques at Run Time	316	(4)
Technology Innovations for Low-Power Design	320	(1)
Novel Device Technologies	320	(1)
Assembly Technology Innovations	321	(1)
Perspectives for Future Ultralow-Power Design	321	(10)
Subthreshold Circuit Operation	322	(1)
Fault-Tolerant Design	322	(1)
Asynchronous versus Synchronous Design	323	(1)
Gate-Induced Leakage Suppression Schemes	323	(1)
References	324	(7)
PART III IMPACT OF PHYSICAL DESIGN ON MANUFACTURING/YIELD AND PERFORMANCE
Design for Manufacturability	331	(12)
Introduction	331	(1)
Comparison of Optimal and Suboptimal Layouts	332	(6)
Global Route DFM	338	(1)
Analog DFM	339	(2)
Some Rules of Thumb	341	(1)
Summary	342	(1)
References	342	(1)
Design for Variability	343	(46)
Impact of Variations on Future Design	343	(4)
Parametric Variations in Circuit Design	343	(2)
Impact on Circuit Performance	345	(2)
Strategies to Mitigate Impact Due to Variations	347	(29)
Clock Distribution Strategies to Minimize Skew	347	(4)
SRAM Techniques to Deal with Variations	351	(10)
Analog Strategies to Deal with Variations	361	(9)
Digital Circuit Strategies to Deal with Variations	370	(6)
Corner Modeling Methodology for Nano-CMOS Processes	376	(5)
Need for Statistical Models	376	(2)
Statistical Model Use	378	(3)
New Features of the BSIM4 Model	381	(4)
Halo/Pocket Implant	381	(1)
Gate-Induced Drain Leakage and Gate Direct Tunneling	382	(1)
Modeling Challenges	383	(1)
Model-Specific Issues	384	(1)
Model Summary	385	(1)
Summary	385	(4)
References	385	(4)
Index	389