Nano-CMOS Design for Manufacturability : Robust Circuit and Physical Design for Sub-65nm Technology Nodes

by Ban P. Wong (NVIDIA Corporation); Anurag Mittal (Virage Logic, Inc.); Greg W. Starr (Xilinx Corporation); Franz Zach (Invarium); Victor Moroz (Synopsys ); Andrew Kahng (University of California at San Diego; Blaze Technologies)

• ISBN13: 9780470382813
• ISBN10: 0470382813
• Format: eBook
• Copyright: 2008-12-01
• Publisher: Wiley-Interscience

Summary

This book is the sequel to Nano-CMOS Circuit and Physical Design, taking design to technology nodes beyond 65nm geometries. It examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. It also tackles complex issues in the design process and introduces several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions.

Table of Contents

Introduction

DFM - Value proposition

Deficiencies in Boolean-based Design Rules in the sub-wavelength regime [6]

Impact of Variability on Yield and Performance

The industry challenge - disappearing process window

Mobility enhancement techniques - a new source of variability induced by design process interaction

Design dependency of chip surface topology

Newly exacerbated narrow width effect in nano-CMOS nodes

Well proximity effect

Scaling beyond 65nm drives the need for model based DFM solutions

Summary

Newly Exacerbated Effects

Lithography related Aspects of DFM

Economic motivations for DFM

Lithographic tools and techniques for advanced technology nodes

Lithography limited yield

Lithography driven DFM Solutions

Interaction of layout with transistor performance and stress engineering techniques

Introduction

Impact of stress on transistor performance

Stress propagation

Stress sources

Introducing stress into transistors

Design Solutions

Signal and Power Integrity

Introduction

Interconnect Resistance, Capacitance and Inductance

Inductance Effects on Interconnect

Analog and Mixed Signal Circuit Design for Yield and Manufacturability

Introduction

Guidelines

Device Selection

Device Size Heart Beat

Device Matching

Design Guidelines

Layout Guidelines

Test

Design for Variability, Performance and Yield

Introduction

Impact of variations (introduced by both process and circuit operation) on the design

Some Parametric Fluctuations with new implications for design

Process Variations in Interconnects

Impact of Deep Sub-Micron Integration in SRAMs

Impact of Layout Styles on Manufacturability, Yield and Scalability

Design for variations

Summary

The Road To DFM

Nano-CMOS design tools: Beyond model-based analysis and correction

Introduction

Electrical Design for Manufacturability (DFM)

Criticality Aware DFM

On Guardbands, Statistics, and Gaps

Opportunistic Mindsets

Futures at = 45nm

Summary

References

Table of Contents provided by Publisher. All Rights Reserved.