Nanometer Technology Designs

While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip defects. For nanometer technology designs, the traditional test methods cannot ensure a high quality level of chips, and at-speed tests using path and transition delay fault model have become a requirement in technologies below 180nm.

Introduction	p. 1
Introduction to VLSI Testing	p. 1
Defects	p. 3
Fault Models	p. 4
Types of Defects	p. 6
Types of Testing	p. 8
Classification Based of Paradigm of Testing	p. 8
Classification Based on Measurement Parameters	p. 11
Voltage-Based Testing	p. 12
Current-Based Testing	p. 14
System-on-Chip (SoC)	p. 15
SoC Testing	p. 15
SoC Test is Expensive	p. 15
SoC Tester: An Example	p. 16
Design For Testability (DFT)	p. 17
DFT Techniques	p. 18
Built-In Self-Test (BIST)	p. 18
Scan or Full Scan	p. 19
Boundary Scan (BS)	p. 21
Delay Fault Testing	p. 22
Path-Delay Faults	p. 23
Transition Delay Faults	p. 24
References	p. 26
At-speed Test Challenges for Nanometer Technology Designs	p. 29
Technology Scaling Effects	p. 29
Crosstalk Effects	p. 31
Power Supply Noise Effects	p. 32
Process Variations Effects	p. 35
Thermal Effects	p. 36
Statistical Analysis	p. 37
High Quality Test Patterns	p. 37
Small Delay Defects	p. 38
Using Low-Cost Testers to Reduce Capital Test Cost	p. 39
Local At-Speed Scan Enable Generation	p. 40
At-Speed I/O Testing	p. 40
References	p. 40
Local At-Speed Scan Enable Generation Using Low-Cost Testers	p. 45
Introduction	p. 46
A Big Picture of Low-cost Testers	p. 49
Background and Motivation	p. 50
Local Scan Enable Signal Generation	p. 54
Last Transition Generator (LTG)	p. 55
Operation of LTG Cell	p. 57
DFT Architecture	p. 59
Multiple Clock Domain Analysis	p. 63
LTG Insertion Flow	p. 64
ATPG	p. 65
Experimental Results	p. 67
Summary	p. 70
References	p. 71
Enhanced Launch-Off-Capture	p. 73
Introduction	p. 74
Overview of Enhanced LOC Method	p. 77
Enhanced Launch-off-Capture	p. 78
Local Scan Enable Signal (LSEN) Generation	p. 82
Local Scan Enable Generator (LSEG)	p. 83
Operation of LSEG Cell	p. 85
Scan Insertion and ATPG Flow	p. 85
Test Architecture	p. 85
Test Synthesis and ATPG	p. 87
Case Study	p. 89
Analysis of ELOC Detected Additional Faults	p. 91
Experimental Results	p. 94
Summary	p. 97
References	p. 98
Hybrid Scan-Based Transition Delay Test	p. 101
Introduction	p. 102
Overview of the Hybrid Method	p. 103
Motivation	p. 103
Local Scan Enable Signal (LSEN) Generation	p. 106
Local Scan Enable Generator (LSEG) Cells	p. 106
Slow Scan Enable Generator (SSEG)	p. 106
Fast Scan Enable Generator (FSEG)	p. 107
Operation of LSEG cells	p. 108
Flip-Flop Selection: ATPG-Based Controllability/Observability Measurement	p. 108
CASE Study: DFT Insertion, ATPG Flow and Fault Analysis	p. 110
Test Architecture	p. 110
Case Study	p. 111
DFT Insertion Based on Controllability/Observability Measure	p. 112
ATPG	p. 114
Analysis of Extra Detected Faults	p. 115
Experimental Results	p. 116
Summary	p. 118
References	p. 118
Avoiding Functionally Untestable Faults	p. 121
Introduction	p. 121
Overview of the Framework	p. 123
Functionally Untestable Fault Identification	p. 125
Constraint Generation, Minimization, and Realization	p. 127
Constraint Generation	p. 128
Constraint Minimization	p. 128
Constraint Realization	p. 129
Framework Implementation	p. 130
Analysis	p. 131
Summary	p. 133
References	p. 133
Screening Small Delay Defects	p. 135
Introduction	p. 136
Overview of the Proposed Timing-based Pattern Generation Procedure	p. 139
Path Length and Pattern Delay Analysis	p. 140
Endpoint Definition	p. 142
Pattern Generation	p. 142
Pattern Selection	p. 145
Experimental Results	p. 147
Pre-processing Phase	p. 147
Pattern Generation and Selection Phase	p. 149
Summary	p. 152
References	p. 154
Faster-Than-At-Speed Test Considering IR-drop Effects	p. 157
Introduction	p. 158
Overview of the Faster-Than-At-Speed Test Technique	p. 160
Case Study: Design Implementation	p. 160
Test Pattern Delay Analysis	p. 162
Dynamic IR-drop Analysis at Functional Speed	p. 164
Dynamic IR-drop Analysis at Faster-than-at-speed Test	p. 166
Pattern Generation Framework	p. 168
Pattern Grouping	p. 168
Estimation of Performance Degradation	p. 169
Experimental Results	p. 173
Summary	p. 174
References	p. 174
IR-drop Tolerant At-speed Test Pattern Generation	p. 177
Introduction	p. 177
Overview of the IR-drop Tolerant Pattern Generation Method	p. 179
Case Study 1: ITC'99 Benchmark b19	p. 179
Physical Design Implementation	p. 180
Statistical IR-drop Analysis	p. 181
Dynamic IR-drop Analysis	p. 182
Average Power Model	p. 185
Pattern Generation Framework	p. 186
Experimental Results	p. 190
Case Study 2: Cadence SOC Design 'Turbo-Eagle'	p. 190
Test Strategy using Statistical IR-drop Analysis	p. 193
Switching Cycle Average Power (SCAP) Model	p. 196
Fault List Manipulation and Pattern Generation	p. 197
Experimental Results	p. 198
Summary	p. 204
References	p. 204
Pattern Generation for Power Supply Noise Analysis	p. 207
Introduction	p. 207
Overview of the Method	p. 209
Power Supply Noise (PSN) Model	p. 209
Pattern Generation	p. 212
Timing of Switching Events	p. 212
Preprocessing Phase	p. 215
Algorithm	p. 215
Pseudocode	p. 216
Example	p. 216
Experimental Results	p. 219
Summary	p. 220
References	p. 220
Delay Fault Testing in Presence of Maximum Crosstalk	p. 223
Technology Scaling Effect on Crosstalk	p. 223
Overview of the Method	p. 227
Preliminary Analysis: Proximity and Transition Direction	p. 227
Victim/Aggressor Proximity	p. 228
Victim/Aggressor Transition Direction	p. 228
Inducing Coupling Effects on Critical Paths	p. 229
Path Segmentation and Coupling	p. 229
Inducing Coupling Effects	p. 231
Pattern Generation Flow with Neighboring Crosstalk Sensitization	p. 232
Parasitic Extraction	p. 233
Critical Path Identification and Segmentation	p. 234
Test Pattern Generation	p. 235
Experimental Results and Analysis	p. 235
Summary	p. 238
References	p. 239
Testing SoC Interconnects for Signal Integrity	p. 241
Introduction	p. 241
Technology Scaling Effects on Signal Integrity	p. 241
Overview	p. 243
Overview	p. 247
Testing Interconnects Using Multiple Transition (MT) Fault Model	p. 247
Enhanced Boundary Scan Cells	p. 252
Test Architecture	p. 259
Implementation and Simulation Results	p. 264
Testing Interconnects Using MA Model	p. 268
Test Data Compression	p. 269
EX-SITEST Instruction and Test Process	p. 271
Results	p. 271
Summary	p. 273
References	p. 273
Index	p. 277
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