Network-on-Chip Architectures

by Nicopoulos, Chrysostomos; Narayanan, Vijaykrishnan; Das, Chita R.

• ISBN13: 9789048130306
• ISBN10: 9048130301
• Format: Hardcover
• Copyright: 2009-10-01
• Publisher: Springer Verlag

Summary

The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.

Table of Contents

Introduction	p. 1
The Diminishing Returns of Instruction-Level Parallelism	p. 1
The Dawn of the Communication-Centric Revolution	p. 2
The Global Wiring Challenge	p. 2
The Network-on-Chip (NoC) Solution	p. 4
Overview of Research	p. 6
Legend for Figs. 1.4 and 1.5	p. 7
A Baseline NoC Architecture	p. 13
MICRO-Architectural Exploration
ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]	p. 19
Importance of Buffer Size and Organization	p. 19
Related Work in Buffer Design	p. 22
The Proposed Dynamic Virtual Channel Regulator (ViChaR)	p. 24
Variable Number of Virtual Channels	p. 27
ViChaR Component Analysis	p. 30
Simulation Results	p. 35
Simulation Platform	p. 35
Analysis of Results	p. 35
Chapter Summary	p. 39
RoCo: The Row-Column Decoupled Router - A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]	p. 41
Introduction and Motivation	p. 41
Related Work in Partitioned Router Architectures	p. 43
The Proposed Row-Column (RoCo) Decoupled Router	p. 44
Row-Column Switch	p. 44
Blocking Delay	p. 48
Concurrency Control for High-Contention Environments	p. 50
Flexible and Reusable On-Chip Communication	p. 51
Fault-Tolerance Through Hardware Recycling	p. 51
Performance Evaluation	p. 56
Simulation Platform	p. 56
Energy Model	p. 57
A Performance, Energy, and Fault-Tolerance (PEF) Metric	p. 57
Performance Results	p. 58
Chapter Summary	p. 62
Exploring Faulto Tolerant Network-on-Chip Architectures [37]	p. 65
Introduction and Motivation	p. 65
Simulation Platform Preliminaries	p. 67
Handling Link Soft Faults	p. 68
Flit-Based HBH Retransmission Scheme	p. 69
Deadlock Recovery	p. 72
Handling Soft Errors in Intra-Router Logic	p. 77
Virtual Channel Arbiter Errors	p. 78
Routing Computation Unit Errors	p. 80
Switch Allocator Errors	p. 81
Crossbar Errors	p. 83
Retransmission Buffer Errors	p. 83
Handshaking Signal Errors	p. 83
Handling Hard Faults	p. 83
Proximity-Aware (PA) Fault-Tolerant Routing Algorithm	p. 84
Extension of PA Routing for Hot-Spot Avoidance	p. 86
Service-Oriented Networking (SON)	p. 88
SON - Direction Lookup Table (DLT) and Service Information Provider (SIP)	p. 89
Chapter Summary	p. 91
On the Effects of Process Variation in Network-on-Chip Architectures [45]	p. 93
Introduction and Motivation	p. 93
Related Work in Process Variation (PV)	p. 94
The Impact of PV on NoC Architectures	p. 95
Evaluation Platform	p. 95
PV Effects on Router Components	p. 98
The Proposed SturdiSwitch Architecture	p. 105
IntelliBuffer: A Leakage-Aware Elastic Buffer Structure	p. 106
VA Compaction Mechanism	p. 108
SA Folding Mechanism	p. 111
Chapter Summary	p. 115
Macro-Architectural Exploration
The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]	p. 119
Introduction and Motivation	p. 119
Exploration of Existing On-Chip Bus Architectures	p. 121
Traditional Bus Architectures	p. 121
TDMA Buses and Hybrid Interconnects	p. 123
Constraints of Traditional Buses	p. 124
CDMA Interconnects	p. 125
The Dynamic Time-Division Multiple-Access (dTDMA) Bus	p. 127
Operation of the Dynamic Timeslot Allocation	p. 128
Implementation of the dTDMA Bus	p. 129
Comparison with a Traditional Bus Architecture	p. 130
dTDMA Bus Performance	p. 132
Comparison with Networks-on-Chip	p. 138
Experimental Setup	p. 138
Results	p. 139
Interconnect Hybridization	p. 141
Affinity Grouping	p. 142
Simulation Methodology	p. 143
Hybridization Results	p. 144
Chapter Summary	p. 146
Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]	p. 147
Introduction and Motivation	p. 149
Background	p. 149
NUCA Architectures	p. 150
Network-In-Memory (NetInMem)	p. 150
Three-Dimensional (3D) Design and Architectures	p. 151
A 3D NetInMem Architecture	p. 153
The dTDMA Bus as a Communication Pillar	p. 155
CPU Placement	p. 157
3D L2 Cache Management	p. 162
Processors and L2 Cache Organization	p. 162
Cache Management Policies	p. 163
Experimental Evaluation	p. 164
Methodology	p. 164
Results	p. 166
Chapter Summary	p. 169
A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]	p. 171
Introduction and Motivation	p. 173
Three-Dimensional Network-on-Chip Architectures	p. 176
A 3D Symmetric NoC Architecture	p. 176
The 3D NoC-Bus Hybrid Architecture	p. 177
A True 3D NoC Router	p. 179
A Partially-Connected 3D NoC Router Architecture	p. 182
The Proposed 3D Dimensionally-Decomposed (DimDe) NoC Router Architecture	p. 182
Performance Evaluation	p. 190
Simulation Platform	p. 190
Energy Model	p. 191
Performance Results	p. 191
Chapter Summary	p. 196
Digest of Additional NoC MACRO-Architectural Research	p. 199
A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects [42]	p. 199
Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects [46]	p. 201
Exploring the Effects of Data Compression in NoC Architectures [47]	p. 203
Conclusions and Future Work	p. 207
References	p. 211
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