Networks on Chip

by Jantsch, Axel; Tenhunen, Hannu

• ISBN13: 9781402073922
• ISBN10: 1402073925
• Format: Hardcover
• Copyright: 2003-02-01
• Publisher: Kluwer Academic Pub

Summary

Networks on Chip presents a variety of topics, problems and approaches with the common theme to systematically organize the on-chip communication in the form of a regular, shared communication network on chip, an NoC for short. As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation. The book is organized in three parts. The first deals with system design and methodology issues. The second presents problems and solutions concerning the hardware and the basic communication infrastructure. Finally, the third part covers operating system, embedded software and application. However, communication from the physical to the application level is a central theme throughout the book. The book serves as an excellent reference source and may be used as a text for advanced courses on the subject.

Table of Contents

Preface	vii
Part I System Design and Methodology
Will Networks on Chip Close the Productivity Gap?	3	(16)
Axel Jantsch
Hannu Tenhunen
A Design Methodology for NoC-based Systems	19	(20)
Juha-Pekka Soininen
Hannu Heusala
Mapping Concurrent Applications onto Architectural Platforms	39	(22)
Andrew Mihal
Kurt Keutzer
Guaranteeing The Quality of Services in Networks on Chip	61	(24)
Kees Goossens
John Dielissen
Jef van Meerbergen
Peter Poplavko
Andrei Radulescu
Edwin Rijpkema
Erwin Waterlander
Paul Wielage
Part II Hardware and Basic Infrastructure
On Packet Switched Networks for On-chip Communication	85	(22)
Shashi Kumar
Energy-reliability Trade-off for NoCs	107	(24)
Davide Bertozzi
Luca Benini
Giovanni De Micheli
Testing Strategies for Networks on Chip	131	(22)
Raimund Ubar
Jaan Raik
Clocking Strategies for Networks on Chip	153	(20)
Johnny Oberg
A Parallel Computer as a NoC Region	173	(20)
Martti Forsell
An IP-Based On-Chip Packet-Switched Network	193	(24)
Ilkka Saastamoinen
David Siguenza-Tortosa
Jari Nurmi
Part III Software and Application Interfaces
Beyond the von Neumann Machine: Communication as the Driving Design Paradigm for MP-SoC from Software to Hardware	217	(22)
Eric Verhulst
NoC Application Programming Interfaces	239	(22)
Zhonghai Lu
Raimo Haukilahti
Multi-level Software Validation for NoC	261	(20)
Sungjoo Yoo
Gabriela Nicolescu
Iuliana Bacivarov
Wassim Youssef
Aimen Bouchhima
Ahmed A. Jerraya
Software for Multiprocessor Networks on Chip	281
Miltos Grammatikakis
Marcello Coppola
Fabrizio Sensini