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Manzur Gill, PhD, is Chief Advancement Officer and Professor of Physics at Forman Christian College, Lahore, in Pakistan. Dr. Gill has more than twenty-five years of experience in high-tech industry and nonvolatile memory development, has authored over thirty technical publications in international journals, and holds over seventy-five patents.
Foreword | |
Preface | |
Contributors | |
Introduction to Nonvolatile Memory | |
Introduction | |
Elementary Memory Concepts | |
Unique Aspects of Nonvolatile Memory | |
Flash Memory and Flash Cell Variations | |
Semiconductor Device Technology Generations | |
Flash Memory Applications | |
Introduction | |
Code Storage | |
Data Storage | |
Code+Data Storage | |
Conclusion | |
Memory Circuit Technologies | |
Introduction | |
Flash Cell Basic Operation | |
Flash Memory Architecture | |
Redundancy | |
Error Correction Coding (ECC | |
Design for Testability (DFT | |
Flash-Specifi c Circuit Techniques | |
Physics of Flash Memories | |
Introduction | |
Basic Operating Principles and Memory Characteristics | |
Physics of Programming and Erase Mechanisms | |
Physics of Degradation and Disturb Mechanisms | |
Conclusion | |
Nor Flash Stacked and Split-Gate Memory Technology | |
Introduction | |
ETOX Flash Cell Technology | |
SST SuperFlash EEPROM Cell Technology | |
Reliability Issues and Solutions | |
Applications | |
NAND Flash Memory Technology | |
Overview of NAND EEPROM | |
NAND Cell Operation | |
NAND Array Architecture and Operation | |
Program Threshold Control and Program Vt Spread Reduction | |
Process and Scaling Issues | |
Key Circuits and Circuit/Technology Interactions | |
Multilevel NAND | |
DINOR Flash Memory Technology | |
Introduction | |
DINOR Operation and Array Architecture | |
DINOR Technology Features | |
DINOR Circuit for Low-Voltage Operation | |
Background Operation Function | |
P-Channel DINOR Architecture | |
P-Channel Flash Memory Technology | |
Introduction | |
Device Structure | |
Operations of P-Channel Flash | |
Array Architecture of P-Channel Flash | |
Evolution of P-Channel Flash | |
Processing Technology for P-Channel Flash | |
Embedded Flash Memory | |
Introduction | |
Embedded Flash Versus Stand-Alone Flash Memory | |
Embedded Flash Memory Applications | |
Embedded Flash Memory Cells | |
Embedded Flash Memory Design | |
Tunnel Dielectrics for Scaled Flash Memory Cells | |
Introduction | |
SiO2 as Tunnel Dielectric-Historical Perspective | |
Early Work on Silicon Nitride as a Tunnel Dielectric | |
Jet-Vapor Deposition Silicon Nitride Deposition | |
Properties of Gate-Quality JVD Silicon Nitride Films | |
Deposited Silicon Nitride as Tunnel Dielectric | |
N-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric | |
P-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric | |
Reliability Concerns Associated with Hot-Hole Injection | |
Tunnel Dielectric for SONOS Cell | |
Prospects for High-K Dielectrics | |
Tunnel Barrier Engineering with Multiple Barriers | |
Summary | |
Flash Memory Reliability | |
Introduction | |
Cycling-Induced Degradations in Flash Memories | |
Flash Memory Data Retention | |
Flash Memory Disturbs | |
Stress-Induced Tunnel Oxide Leakage Current | |
Special Reliability Issues for Poly-to-Poly Erase and Source-Side Injection Program | |
Process Impacts on Flash Memory Reliability | |
High-Voltage Periphery Transistor Reliability | |
Design and System Impacts on Flash Memory Reliability | |
Flash Memory Reliability Screening and Qualifi cation | |
For Further Study | |
Multilevel Cell Digital Memories | |
Introduction | |
Pursuit of Low-Cost Memory | |
Multibit Storage Breakthrough | |
View of MLC Today | |
Low-Cost Design Implementation | |
Low-Cost Process Manufacturing | |
Standard Product Feature Set | |
Further Reading: Multilevel Flash Memory and Technology Scaling | |
Conclusion | |
Alternative Memory Technologies | |
Introduction | |
Limitations of Flash Memory | |
NROM Memories | |
Ferroelectric Memories | |
Magnetic Memories | |
Single-Electron and Few-Electron Memories | |
Resistive and Hybrid CMOS/Nanodevice Memories | |
NOVORAM/FRAM Cell and Architecture | |
Phase Change Memories | |
Index | |
About the Editors | |
Table of Contents provided by Publisher. All Rights Reserved. |
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