Nonvolatile Semiconductor Memory Technology A Comprehensive Guide to Understanding and Using NVSM Devices

by Brown, William D.; Brewer, Joe

• ISBN13: 9780780311732
• ISBN10: 0780311736
• Edition: 1st
• Format: Hardcover
• Copyright: 1997-10-29
• Publisher: Wiley-IEEE Press

Summary

"Complete dependence on semiconductor vendors' application notes and data sheets is now a thing of the past thanks to this all-in-one comparison text on nonvolatile semiconductor memory (NVSM) technology. Working electronics engineers can now refer to this book to access the technical data and applications-focused perspective they need to make intelligent decisions regarding the selection, specification, procurement, and application of NVSM devices. The most comprehensive book in the field, NONVOLATILE SEMICONDUCTOR MEMORY TECHNOLOGY gathers expertly-written information scattered throughout device literature in a single, well-balanced volume. This book features an in-depth overview accompanied by applications-oriented chapters on device reliability and endurance, radiation tolerance, as well as device physics and design. It is an essential reference for electronics engineers." Sponsored by: IEEE Components, Packaging, and Manufacturing Technology Society, IEEE Solid-State Circuits Council/Society.

Author Biography

About the Editors William D. Brown is a university professor and head of the Department of Electrical Engineering at the University of Arkansas. As a Member of the Technical Staff at Sandia Laboratories in Albuquerque, NM, from 1969-1977, Dr. Brown initiated Sandias research and development effort on metal-nitride-oxide-silicon (MNOS) device technology. After joining the faculty at the University of Arkansas in 1977, his nonvolatile semiconductor memory research concentrated on the synthesis and characterization of plasma-enhanced chemical vapor deposited (PECVD) silicon nitride for application in MNOS and SNOS memory devices. Dr. Brown has served on IEEE NVM standards committees, and he is an organizer and participant in the IEEE International Nonvolatile Memory Technology Conference and its precursor conferences.

Table of Contents

List of Contributors	xv
List of Acronyms	xvii
Foreword	xxi
Basics of Nonvolatile Semiconductor Memory Devices	1	(88)
G. Groeseneken
H.E. Maes
J. Van Houdt
J.S. Witters
Introduction	1	(3)
Basic Principles and History of NVM Devices	4	(5)
Basic Operating Principle	4	(2)
Short Historical Review	6	(3)
Basic Programming Mechanisms	9	(16)
Fowler--Nordheim Tunneling	10	(4)
Polyoxide Conduction	14	(3)
Hot-Electron Injection	17	(4)
Source-Side Injection	21	(2)
Direct Band-to-Band Tunneling and Modified Fowler--Nordheim Tunneling	23	(2)
Basic NVSM Memory Products	25	(7)
Eprom/Otp	25	(2)
Eeprom	27	(3)
Flash EEPROM	30	(1)
NOVRAM	31	(1)
Basic NVSM Devices Presently in Use	32	(20)
Floating Gate Devices	32	(1)
SIMOS (EPROM, Flash EEPROM)	33	(4)
FLOTOX (EEPROM, NOVRAM)	37	(5)
TPFG (EEPROM, NOVRAM)	42	(2)
Combinations	44	(3)
Charge Trapping Devices	47	(1)
MNOS and SNOS Devices (EEPROM, NOVRAM)	47	(2)
SONOS Device	49	(1)
Ferroelectric Devices	50	(2)
Comparison of the Floating Gate, Charge-Trapping, and Ferroelectric Devices	52	(1)
Basic NVSM Device Equations and Models	52	(14)
The Capacitor Model	53	(4)
I-V Characteristics of Floating Gate Devices	57	(1)
Experimental Determination of the Coupling Factors k and d	58	(4)
Modeling of the Memory Characteristics of Fg-Cells	62	(4)
Modeling of the Memory Characteristics of SNOS and SONOS Devices	66	(1)
Basic NVSM Memory Characteristics	66	(9)
Transient Characteristics	67	(2)
Endurance Characteristics	69	(1)
Floating Gate Devices	69	(4)
Charge-Trapping Devices	73	(1)
Retention Characteristics	73	(1)
Floating Gate Devices	74	(1)
Charge-Trapping Devices	74	(1)
Radiation Aspects of Nonvolatile Memories	75	(14)
SNOS Technology	75	(1)
Floating Gate Technology	76	(2)
Ferroelectric Technology	78	(1)
References	78	(11)
Floating Gate Planar Devices	89	(67)
H.C. Lin
R. Ramaswami
Introduction	89	(1)
Cell Structures and Operations	90	(15)
Structures for Custom IC Applications	99	(6)
Memory Array Circuitry	105	(13)
Charge-Pump Circuits	108	(4)
High-Voltage Load Circuits	112	(3)
Peripheral Control Circuits	115	(3)
Process Technology	118	(12)
Ultrathin Tunnel Dielectric Technology	119	(7)
Floating Gate Doping and Etching	126	(1)
Interpoly Dielectrics	126	(1)
High-Voltage Technology	127	(2)
EEPROM Scaling Considerations	129	(1)
Degradation Mechanisms	130	(13)
Electron Capture and Emission	132	(2)
Hole Generation, Capture, and Emission	134	(1)
Oxide Breakdown	135	(1)
Electron Trapping Breakdown Model	135	(2)
Hole Trapping Breakdown Model	137	(2)
Noncharge-trapping Breakdown Model	139	(1)
Parameter Extraction	139	(4)
Typical Current-Voltage (I-V) Characteristics	143	(13)
Programming I--V Characterstics	143	(4)
Retention Characteristics	147	(2)
References	149	(7)
Floating Gate Nonplanar Devices	156	(33)
H.A.R. Wegener
W. Owen
Introduction	156	(1)
Cell Structures and Operation	157	(13)
General Principles of Opration	157	(1)
Description of Devices	157	(2)
Description of Nonvolatile Writing	159	(2)
Description of Reading	161	(1)
Capacitive Coupling of Voltages	161	(2)
Fowler--Nordheim Emission from Textured Surface Features	163	(3)
Description of Cell Structures	166	(1)
Early Cell	166	(1)
The Direct Write Cell	167	(3)
Process Technology	170	(1)
General Description	170	(1)
High-Voltage Circuitry	170	(1)
Cell Processing	170	(1)
Summary of Production-Level Technology	171	(1)
Memory Array Circuitry	171	(5)
Typical Organization	171	(1)
Nonvolatile Writing	172	(3)
Reading	175	(1)
Typical Operation	175	(1)
Special Features	175	(1)
Degradation Mechanisms	176	(4)
Time-Dependent Dielectric Breakdown (TDDB)	176	(1)
Extrinsic Breakdown	177	(1)
Trap-up	178	(1)
Comparison with Thin Oxide	178	(2)
Typical Characteristics	180	(9)
Performance	180	(1)
Endurance	180	(3)
Retention	183	(2)
Technology Features, Cells, and Capacities	185	(2)
References	187	(2)
Floating Gate Flash Devices	189	(120)
M. Gill
S. Lai
Introduction	189	(5)
Why Flash?	191	(2)
A Brief History of Flash EEPROM	193	(1)
Basics of Program and Erase Operations	194	(6)
Channel Hot-Election (CHE) Programming	194	(3)
Source-Side Hot-Election Programming	197	(1)
Fowler--Nordheim (F--N) Tunneling	198	(1)
Tunnel Programming	199	(1)
Tunnel Erase Through Thin Oxide	199	(1)
Tunnel Erase Through Poly-to-Poly Oxide	200	(1)
Flash Memories with Channel Hot-Electron (CHE) Program and Tunnel Oxide Erase	200	(16)
Positive Source Erase	200	(2)
Positive Drain Erase	202	(1)
Nagative Gate Erase	202	(1)
Negative (Control) Gate, Floating Gate to Source Erase	202	(1)
Negative (Control) Gate, Floating Gate to Drain Erase	203	(1)
Negative (Control) Gate, Floating Gate to Channel Erase	204	(1)
Erase Threshold Control	205	(3)
Erased Vt Spread Reduction	208	(1)
Post-gate Oxide Poly Process	208	(1)
Two-step Erase	209	(1)
Self-convergence Erasing Scheme	209	(4)
Program Disturb Mechanisms	213	(3)
Flash Memories with Channel Hot-Electron Program And Poly-to-Poly Erase	216	(4)
Triple-Poly NOR	217	(1)
Triple-Poly, Virtual Ground Contracless	217	(2)
Cell/Array Architecture	219	(1)
Programming	220	(1)
Erase	221	(1)
Read	222	(1)
Write Inhibit Conditions	222	(1)
The Field-Enhancing Tunneling Injector EEPROM Cell	223	(1)
Cell Structure	223	(3)
Erasing	226	(1)
Erase Disturb	226	(1)
Programming	226	(1)
Program Disturb	227
Flash Memories with Fowler--Nordheim Tunnel Program and Erase	220	(25)
Array Contractless EEPROM (ACEE)	228	(1)
Charge Transfer	229	(1)
Inhibit Condition	229	(1)
Read	229	(1)
The AND Cell	230	(3)
The DINOR Cell	233	(1)
Program/Erase Operation	234	(1)
Cell Structure	234	(1)
Disturb and Endurance Characteristics	235	(1)
Virtual Ground DINOR	235	(2)
HICR Flash Memory Cell	237	(2)
Program Disturbance	239	(2)
NAND	241	(1)
NAND Structure	241	(1)
NAND Operation	242	(2)
Disturb Mechanisms	244	(1)
Special Features	244	(1)
Special and Advanced Cell Structures	245	(10)
Source-Coupled Split-Gate (SCSG) Flash EEPROM Cell	245	(1)
Charge Transfer	245	(2)
Inhibit Conditions	247	(1)
Read	247	(1)
High-Injection MOS (HIMOS)	248	(3)
3-D Cell Structures	251	(1)
Trench-Embedded Field-Enhanced Tunneling (TEFET)	251	(1)
3-D Side-Wall Flash EEPPROM Cell	252	(1)
Multielvel Cell	253	(2)
Flash Reliability Issues	255	(26)
Channel Hot-Electron Programming	255	(1)
Electron Trapping (Nox) in Vfg > Vd Regime	255	(3)
Surface State Generation (Nss) in Vfg < Vd Regime	258	(1)
Trap Reduction Through Nitridation	258	(3)
Grounded-Gate Source-Erase-Induced Cell Degradation	261	(1)
Band-to-Band Tunneling Generated Hot Hole	261	(3)
Avalanche Breakdown-Induced Cell Wearout	264	(2)
Reduction of Hot-Hole Injection	266	(1)
Drain-Leakage-Induced Over-Erase	267	(1)
Erratic Bits	267	(2)
Source-Side Injection	269	(1)
Stress-Induced Oxide Leakage	269	(1)
Time-Dependent Dielectric Breakdown (TDDB) under High-Frequency Stress	270	(2)
Poly-to-Poly Erase	272	(1)
Reliability of Interpoly Dielectric	272	(1)
Stacked Gate Write/Erase Endurance	272	(1)
NAND Write/Erase Endurance	272	(2)
Data Retention	274	(5)
Read Disturb	279	(2)
Process Technology	281	(1)
Floating Gate Technology	281	(1)
High-Voltage Technology	282	(1)
Memory Circuitry	282	(7)
Row Decoder Circuits	283	(5)
Erase Circuits	288	(1)
Charge-Pump Circuits	289	(1)
Flash Applications	289	(7)
EPROM Replacement	289	(1)
Code Storage	290	(1)
Automotive Applications	291	(1)
Joint Testability Action Group (JTAG)	291	(1)
Cards	292	(1)
Smart Cards	292	(1)
Look-Up Tables/Data Acquisition	292	(1)
Personal Systems	293	(1)
Analog Applications	293	(1)
Logic	293	(1)
New Architectures	293	(1)
DRAM versus Flash	294	(2)
Conclusions and a Look Into the Future	296	(2)
Flash Market Development Trends	298	(1)
Acknowledgments	298	(11)
References	298	(11)
SONOS Nonvolatile Semiconductor Memories	309	(129)
M.H. White
F.R. Libsch
Introduction	309	(1)
The Sonos Nonvolatile Memory Transistor	310	(22)
Trigate MNOS Memory Cell (3TC)	311	(3)
Trigate Memory Cell Operation	314	(1)
Trigate Memory Cell Electrical Characteristics	315	(1)
Trigate Memory Cell Technology	315	(2)
Pass Gate Memory Cell (2TC)	317	(1)
Pass Gate Memory Cell Operation	318	(2)
Pass Gate Memory Cell Electrical Characteristics	320	(1)
Pass Gate Memory Cell Technology	320	(4)
Split (Merged) Gate Cell (1-1/2TC)	324	(1)
Split Gate Memory Cell Operation	324	(2)
Split Gate Memory Cell Electrical Characteristics	326	(1)
Split Gate Memory Cell Technology	327	(1)
Single-Transistor Memory Cell (1TC)	328	(1)
NVRAM Transistor Cell (SRAM + EEPROM)	328	(1)
NVRAM Cell Operation	329	(1)
NVRAM Cell Electrical Characteristics	330	(1)
NVRAM Cell Technology	331	(1)
Memory Array Circuitry	332	(9)
Trigate Transistor Array	332	(3)
Pass Gate Transistor Array	335	(1)
Split (Merged) Gate Transistory Array	336	(3)
Single-Transistor Array	339	(1)
NVRAM Transistor Array	340	(1)
Degradation Mechanisms	341	(2)
Typical Characteristics	343	(15)
Erase/Write	343	(1)
Retention	344	(1)
Endurance	345	(1)
Radiation Hardness	345	(2)
Low-Voltage Operation	347	(2)
CMOS Compatibility	349	(1)
Scaling Issues	349	(5)
References	354	(4)
Reliability and NVSM Realiability	358	(1)
Y. Hsia
V.C. Tyree
Introduction	358	(4)
Primary Reliability Concerns	362	(18)
Physics of Traps	363	(1)
Charge and Traps in SiO2	363	(6)
Charge and Traps in Si3N4	369	(6)
NVSM Failure Modes	375	(1)
Floating Gate NVSM Devices	375	(5)
Floating Trap NVSM Devices	380	(1)
NVSM Relibility and Applications	380	(24)
Reliability Modeling	385	(2)
Oxide Failure Models	387	(2)
Hot-Carrier Damage Models	389	(1)
Electromigration Models	390	(2)
NVSM Application---Device Design Examples	392	(6)
NVSM Application---Circuit Design Examples	398	(6)
Reliability Testing and Yield	404	(34)
Validation Testing: Reliabilty Assurance in Manufacturing	408	(1)
Accelerated Testing and Its Limitations	409	(1)
The Impact of Choice of Distribution	410	(1)
Recognizing Bimodal Distributions	411	(3)
Hierarchical Calibration: Dealing with Nonideal Data Sets	414	(2)
Isolating Mechanisms---Models and Testing: TDDB	416	(5)
Isolating Mechanisms---Models and Testing: EM	421	(1)
Electromigration Testing Standards: Contact Electromigration	422	(1)
Electromigration Testing Standards: Interconnect Electromigration	422	(3)
Isolating Mechanisms---Models and Testing: HCD	425	(2)
Typical Reliability Data	427	(5)
References	432	(6)
Radition Tolerance	438	(28)
G. Messenger
Introduction	438	(1)
Basic Radiation Considerations	438	(20)
Radiation Environments	438	(1)
Nuclear Weapon Environments	439	(1)
The Natural Space Radiation Environment	440	(2)
Nuclear Power Reactors	442	(1)
Radition Simulations	443	(1)
Displacement Damage	443	(1)
Lifetime Degradation	444	(1)
Carrier Removal	444	(1)
Mobility Degradation	445	(1)
Particle Equivalence	446	(1)
Device Effects	447	(2)
Ionizing Dose Damage	449	(1)
Trapping in Bulk SiO2	449	(1)
Trapping at SiO2-Si Interface	450	(1)
Device Effects	450	(3)
Dose-Rate Effects	453	(1)
Generation Rates	454	(1)
IEMP	454	(1)
Burnout	454	(1)
Latchup	455	(1)
Upset	456	(1)
Singe-Event Phenomena	456	(1)
Single-Event Latchup/Burnout	457	(1)
Single-Event Upset	457	(1)
Floating Gate Radiation Effects	458	(3)
Basic Effects	458	(1)
Response to Ionizing Radiation	459	(1)
Hardening of Floating Gate Devices	460	(1)
Dose-Rate Response	460	(1)
Other Radiation Effects	460	(1)
System Considerations	461	(1)
SNOS Radiation Effects	461	(3)
Basic Effects	461	(1)
Response to Ionizing Radition	462	(1)
Response to Dose Rate	463	(1)
Response to Neutron Fluence	463	(1)
Hardening of SNOS Memories	464	(1)
Other Nonvolatile Rams	464	(2)
Magnetic RAMs	464	(1)
Static RAMs with Battery Backup	464	(1)
Ferroelectric RAMs	464	(1)
References	465	(1)
Procurement Considerations	466	(17)
D. Sweetman
Introduction	466	(1)
Commercial Specification Practices	467	(8)
Data Sheets	467	(4)
Reliability Parameters	471	(3)
Warranty Policies	474	(1)
Critical Device Parameters	475	(1)
Electrical	475	(1)
Mechanical/Visual	476	(1)
Reliability	476	(1)
Manufacturer's Screening	476	(2)
Electrical	477	(1)
Reliability	477	(1)
Qualification Testing	478	(3)
Characterization	478	(1)
Verification	479	(2)
Summary	481	(2)
References	481	(2)
Bibliography	483	(72)
W.D. Brown
Index	555	(34)
Editors' Biographies	589